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EP0096333A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Full adder

Assignee: Toshiba Corp
•
Filing: 1983-05-30
•
Granted: —
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Expires: 2003-05-30
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Abstract

Abstract A full adder is disclosed which comprises a first exclusive OR circuit (4) for OR processing a first input signal (DA) and a second input signal (DB), a second exclusive OR gate (6) for OR processing an output signal (E) of the first exclusive OR gate (4) and a third input signal (DC), and select circuit (8) for selecting one of the first and second input signals (DA, DB) and the third input signal (DC) according to a logical level of the output signal (E) of the first exclusive OR gate (4). A sum signal of the first to third input signals (DA, DB and DC) is obtained by the first exclusive Or means (4) and the second exclusive OR means (6). The select means (8) selects either the first or second input signal (DA or DB) or the output signal (E) of the third input signal (DC) according to a logical level of the output signal (E) of the first exclusive OR means (4). The selected signal is used as a carry signal.

Inventors

  • 👤 Kazuo Suganuma

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 11:11
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 131 words
A full adder characterized by comprising: first exclusive OR processing means (4) for OR processing a first input signal (DA) and a second input signal -(DB); second exclusive OR processing means (6) for OR processing an output signal (E) of said first exclusive OR processing means (4) and a third input signal (DC); select means (8) for selecting one of said first and second input signals (DA, DB) and said third input signal DC according to a logical level of the output signal (E) of said first exclusive OR processing means (4) ; whereby a sum signal (So) of said first, second and third input signals (DA, DB and DC) from said second exclusive OR processing means (6) and a carry signal (Co) are taken out from said select means (8).
Claim 2
Dependent Claim 131 words
A full adder characterized by comprising: first exclusive OR processing means (4) for OR processing a first input signal (DA) and a second input signal -(DB); second exclusive OR processing means (6) for OR processing an output signal (E) of said first exclusive OR processing means (4) and a third input signal (DC); select means (8) for selecting one of said first and second input signals (DA, DB) and said third input signal DC according to a logical level of the output signal (E) of said first exclusive OR processing means (4) ; whereby a sum signal (So) of said first, second and third input signals (DA, DB and DC) from said second exclusive OR processing means (6) and a carry signal (Co) are taken out from said select means (8).
Claim 3
Dependent Claim 111 words
A full adder according to claim 1, characterized in that said select means (8) includes first and second MOS FETs of different channel types (P27, N27) which receive at their gates the output signal (E) of said first exclusive OR processing means (4) and are interconnected at ends thereof, one of said first and second input signals (DA, DB) is input to the other end of said first MOS FET (P27), said third input signal (DC) is applied to the other end of said second MOS FET (27), and a node of said interconnected ends of said first and second MOS FETs (P27, N27) serves as a signal output point (9).
Claim 4
Dependent Claim 173 words
A full adder according to claim 1, characterized in that said select means (8) includes a first parallel circuit including first and second channel type MOS FETs (P27, N29) interconnected in parallel which respectively receive at their gates the output signal (E) of said first exclusive OR processing means (4) and the inverted signal of the output signal (E) and a second parallel circuit connected in series to said first parallel circuit and including third and fourth MOS FETs (N27, P29) of the second and first channel type which are interconnected in parallel, said third and fourth MOS PETs respectively receiving at their gates the output signal (E) of said first exclusive OR processing means (4) and the inverted signal of the output signal (E), wherein the other end of said first parallel circuit receives said first and second input signals (DA, DB), the other end of said second parallel circuit receives said third input signal (DC), and a node of said first and second parallel circuits serves as a signal output point.

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