Bus system

Abstract

Abstract This bus system is intended for a bi-directional transmission of data between a central processor and a peripheral station. In a peripheral input/output circuit (PES), a decoder circuit (Di, Wi) exists which generates two output signals (Ai, Wi) from the address codeword and an additionally redundantly transmitted control address codeword, an additional register selector (RW) being connected downstream which only outputs the control bits (Sm, Sn, Sp, Sq) when both output signals (Ai, Wi) are present. The input/output circuit (PES) is followed by a control stage (KS) in which the individual bits of the sequence of data words are compared bit by bit with the individual bits of an additionally redundantly transmitted sequence of control data words and which in each case only forwards a data bit when one data bit each of both sequences is present. This ensures data protection of the same value over the entire system. <IMAGE>

Inventors

• 👤 Kurt Husi

Bibliographic Details