EP0095598A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multiprocessor with independent direct cache-to-cache data transfers
Assignee: International Business Machines Corp
•
Filing: 1983-05-06
•
Granted: —
•
Expires: 2003-05-06
Abstract
Abstract In a data processing system having multiple processors with individual cache stores, a cross-interrogation is made in other caches if requested data is not found in the local associated cache. Data paths (67, 74, 83, 86, 201, 202, 203, 207, 208) and communication controls (20, 21, 22, 23, 50, 76, 77) are provided to enable direct cache-to-cache and cache-to-channel data transfers thus saving main storage accesses and the necessity to wait for main storage availability.
Inventors
- 👤 Matthew Anthony Krygowski
- 👤 Benedicto Umberto Messina
- 👤 William Dean Silkman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:16
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0822
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
231 words
A multiprocessor system having plural central processing units CPU, at least one I/O channel processor, and a shared main storage, in which each system CPU has a cache storage for receiving and casting-out lines of data from and to main storage, cache directory means (11, 209, 210) being provided for each cache, and any cache becoming a requesting cache when it does not contain data requested by an associated CPU, which fact is signalled as a missed request by cache controls (BCE 1...BCE4), said multiprocessor system further comprising cross-interrogation means (20, 45, 47, 51, 58) for receiving each missed request and for searching the directory means of all other caches to find a data line containing the requested data, any such line if found being designated as hit line and the cache containing it being designated as hit cache, characterized by - control communication means (18, 19, 21, 22, 23, 25, 34, 59, 61, 66, 71, 72, 76) associated with the cross-interrogation means for control signalling to the hit cache controls and to the requesting cache controls that a hit line is to be transferred, and - data bus means (74, XP1...XP4, 83, 86, 101, 102, 201, 202, 301...314) for transferring the hit line of data from the hit cache to the requesting cache without passing the data through main storage or synchronizing the transfer with the availability of main storage.
Claim 2
Dependent Claim
231 words
A multiprocessor system having plural central processing units CPU, at least one I/O channel processor, and a shared main storage, in which each system CPU has a cache storage for receiving and casting-out lines of data from and to main storage, cache directory means (11, 209, 210) being provided for each cache, and any cache becoming a requesting cache when it does not contain data requested by an associated CPU, which fact is signalled as a missed request by cache controls (BCE 1...BCE4), said multiprocessor system further comprising cross-interrogation means (20, 45, 47, 51, 58) for receiving each missed request and for searching the directory means of all other caches to find a data line containing the requested data, any such line if found being designated as hit line and the cache containing it being designated as hit cache, characterized by - control communication means (18, 19, 21, 22, 23, 25, 34, 59, 61, 66, 71, 72, 76) associated with the cross-interrogation means for control signalling to the hit cache controls and to the requesting cache controls that a hit line is to be transferred, and - data bus means (74, XP1...XP4, 83, 86, 101, 102, 201, 202, 301...314) for transferring the hit line of data from the hit cache to the requesting cache without passing the data through main storage or synchronizing the transfer with the availability of main storage.
Claim 3
Dependent Claim
94 words
A multiprocessor system as defined in claim 1, further characterized by - a plurality of output buffers (207, 208), one dedicated output buffer being associated with each cache, - means (67, 81) for copying the hit line from the hit cache into the associated output buffer, - the data bus means (74, 83, 86, 201, 202) transferring the hit line from the output buffer to the requesting cache, - whereby the hit cache can be performing access operations independent of the hit line while the hit line is being transferred to the requesting cache.
Claim 4
Dependent Claim
105 words
A multiprocessor system as defined in claim 1, further characterized by - write control means (31) responsive to the control communication means (18, 19, 21, 23, 25) for marking the received line as changed and exclusive in the directory means (11) of the receiving cache, - if the missed request to the cross-interrogation means (20, 45, 47, 51, 58) was for exclusive (EX) data, and the cross-interrogation means found the hit line changed in the hit cache, - so that no updating data transfer from or to main storage is required for the hit line which is transferred exclusively and changed to the requesting cache.
Claim 5
Dependent Claim
139 words
A multiprocessor system as defined in claim 1, further characterized by - the control communication means (18, 19, 21, 23, 25) reporting the state of a line-changed flag field (CH) for a hit line in the hit cache, and - write control means (31) being provided responsive to the control communication means for marking the received line as exclusive in the directory means (11) of the receiving cache and for setting the line-changed flag field for the received line to the same state as the line-changed flag field reported by the control communication means for the hit line - if the missed request generated to the cross-interrogation means was for readonly (RO) data, - so that no updating data transfer from or to main storage is required for the hit line which is transferred exclusively to the requesting cache.
Claim 6
Dependent Claim
140 words
A multiprocessor system as defined in claim 1, also comprising an instruction element (IE1...IE4) in each CPU for making requests for either exclusive (EX) or readonly (RO) data to an associated cache directory (11), flag fields in each cache directory for indicating an exclusive state EX or a readonly state RO of each line of data being validly held in the associated cache, and means (50, 52) for generating a main storage request for fetching a requested line of data at the time when the cross-interrogation means (20, 45, 47, 51, 58) receives a missed request for the same line of data, further characterized by - means (53) for cancelling the main storage request in response to the control communication means (34, 59) signalling that a hit cache is found with an EX flag indicating the hit line is exclusive.
Claim 7
Dependent Claim
86 words
A multiprocessor system as defined in claim 5, further characterized by - write control means (31, 43, 44) responsive to the control communication means (19, 59) for setting on the state designation in the EX flag field for the transferred hit line in the directory means (11, 209, 210) of the requesting cache, and for invalidating the hit line in the directory means (11, 209, 210) of the hit cache, - whereby the transferred line is available exclusively in the requesting cache after the cache-to-cache transfer.
Claim 8
Dependent Claim
197 words
A multiprocessor system as defined in claim 2, further comprising flag fields with each entry in the cache directory means (11, 209, 210) for indicating an exclusive or readonly state (EX/OR) and a line-changed or not-changed (CH) state of each line of data being validly held in the associated cache, characterized by - means(46, 66, 69, 74, 83, 86, 204) for transferring the hit line to main storage from the associated output buffer (207, 208) after the hit line was transferred from the associated output buffer to the requesting cache, - only when main storage is available for an access, and - only if the missed request issued was for readonly (RO) data and if the line-changed flag field (CH) in the hit cache was found to indicate that the hit line was changed and thus is different from a corresponding line with the same address in main storage, and - means (31, 43, 44) for setting flag fields in the directory means (11, 209, 210) of the requesting cache to readonly state (RO) and not-changed state (CH) to indicate that the received line is the same as the line in main storage with the same address.
Claim 9
Dependent Claim
121 words
A multiprocessor system as defined in claim 1, further characterized by - means (37) for furnishing I/O channel requests for main storage data accesses from a channel to the cross-interrogation means (20, 45, 47, 51, 58) - said control communcation means (21, 22, 23, 59, 66) providing a signal if a hit line has been found for an I/O channel request by the cross-interrogation means in a cache directory (209, 210), and if the line is being transferred to the requesting channel, and by - data bus means (74, 83, 86, 203) for transferring the data from the hit cache to the requesting channel without passing the data through main storage or synchronizing the transfer with the availability of main storage.
Claim 10
Dependent Claim
127 words
A multiprocessor system as defined in claim 8, further characterized by - a plurality of output buffers (207, 208), one output buffer being associated with each cache, - means (67, 81) for copying the hit line from the hit cache into the associated output buffer in response to signalling from the control communication means (23, 66), - said data bus means (74, 83, 86, 203) transferring the hit line from the output buffer to the requesting I/O channel in response to a signal (82) indicating that the hit line is received by the associated output buffer, - whereby the hit cache can be performing access operations independent of the hit line while the hit line is being transferred to the requesting channel from the associated output buffer.
Claim 11
Dependent Claim
111 words
A multiprocessor system as defined in claim 9, further characterized by - means (46, 66, 69, 74, 83, 86, 204) for transferring the hit line from the associated output buffer (207, 208) to main storage - whenever main storage is available and - after the hit line or any part of it was transferred from the associated output buffer to the requesting I/O channel, - whereby the I/O channel can later obtain from main storage any data in the hit line not received by the I/O channel during the cache-to-channel transfer, so that the hit cache is not again disturbed for the same line of data by any other channel request.
Claim 12
Dependent Claim
96 words
A multiprocessor system as defined in claim 1, further characterized in that - the control communication means comprises hit response control means (66) associated with the controls for each CPU cache directory, for generating response signals (81, 82) indicating that the cache controls are complying with a request for furnishing the data of a hit line from the respective hit cache, and that - data switching circuitry (74, XP1...XP4) is provided for connecting a data path from the hit cache to the requesting cache in response to the signals (82) from the hit response control means.
Claim 13
Dependent Claim
79 words
A multiprocessor system as defined in claim 11, further characterized in that - an output buffer (207, 208) is connected to the output of each cache for receiving a hit line in response to the signals (81) from the hit response control means (66), and that - the data switching circuitry (74) is connected between the outputs (83) of plural output buffers (207, 208) and input busses (201, 202, 203, 204) to a plurality of caches and other units.
Claim 14
Dependent Claim
124 words
A multiprocessor system as defined in claim 12, further including a plurality of system control elements (SCE1...SCE4) containing the cross-interrogation means (45, 47, 51), each system control element being directly connected to cache controls (BCE1...BCE4) for a subset of the CPUs, to a main storage section, to an I/O channel processor, and to each other system control element in the multiprocessor system, characterized in that each data switching circuitry further comprises - crosspoint switching means (XP1...XP4) connected at least to the data outputs (83) of the associated output buffers (207, 208), the data input (201, 202) of each directly connected cache controls, the input (204) and output (205) of the associated main storage section, and inputs and outputs to each other system control element.
Claim 15
Dependent Claim
55 words
A multiprocessor system as defined in claim 13, further characterized in that multiple crosspoint switching means (XP1...XP4) are provided in each system control element (SCE1, SCE2) and are so interconnected by busses with the other associated units that multiple parallel data transfer paths via the inputs and/or outputs of the crosspoint switching means are enabled.
Claim 16
Dependent Claim
45 words
A multiprocessor system as defined in claim 13, further characterized in that the crosspoint switching means (XP1...XP4) in the different system control elements (SCE1, SCE2) are interconnected by multiple parallel bus means (101, 102) to enable parallel independent data transfers between the crosspoint switching means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.