Static memory circuit

Claim 2

A static memory circuit comprising a plurality of word lines, a plurality of bit line pairs intersecting with said word lines, a plurality of static-type memory cells arranged at intersections of said word lines and said bit line pairs, a first terminal for receiving a write control signal having a first logic level for designating a read operation and a second logic level for designating a write operation, a second terminal for receiving an input data, and a read circuit responsive to said first logic level of said write signal for reading data out of a selected memory cell, a write circuit coupled to said first and second terminals for applying said input data to a selected memory cell in response to said second logic level of said write signal, said write circuit including a holding circuit for holding said input data at least for a period of said write signal in said second logic level.

Claim 3

The memory circuit according to Claim 1, in which said holding circuit includes a first buffer circuit having an input terminal coupled to said second terminal, a latch circuit, a transfer gate coupled between an output terminal of said first buffer circuit and an input terminal of said latch circuit, a control circuit coupled to said first terminal for conducting said transfer gate in response to said second logic level of said write signal and a second buffer circuit having an input terminal coupled to the output terminal of said latch circuit for generating internal input data to be writen into the selected memory cell.

Claim 4

The memory circuit according to claim 1, in which said read circuit includes a read data line, a plurality of sense amplifiers provided for the respective bit line pairs having output terminals coupled to said read data line, and means for selectively enabling one of said sense amplifiers.

Claim 5

The memory circuit according to Claim 1, in which said write circuit includes a pair of write data lines, a plurality of selection gate pairs each coupled between the corresponding bit line pair and said pair of write data lines, and means for applying output of said data circuit to said pair of write data lines.

Claim 6

A static memory circuit comprising a plurality of static-type memory cells arranged in a matrix form of rows and columns, means for receiving row address signal, means for receiving column address signal, first means responsive to said row address signals for selecting one of said rows, second means for selecting said columns, a first terminal receiving a first control signal having first and second logic levels, a first circuit coupled to said columns for deriving read data from the column selected by said second means in response to said first logic level of said first control signal, a second terminal for receiving input data, a second circuit coupled to said first and second terminals for storing said input data in response to said second logic level of said first control signal, and a third circuit for applying the data stored in said second circuit to the column selected by said second means.

Claim 7

A static memory circuit comprising a plurality of static-type memory cells arranged in a matrix form of rows and columns, means for receiving row address signal, means for receiving column address signal, first means responsive to said row address signals for selecting one of said rows, second means for selecting said columns, a first terminal receiving a first control signal having first and second logic levels, a first circuit coupled to said columns for deriving read data from the column selected by said second means in response to said first logic level of said first control signal, a second terminal for receiving input data, a second circuit coupled to said first and second terminals for storing said input data in response to said second logic level of said first control signal, and a third circuit for applying the data stored in said second circuit to the column selected by said second means.

Claim 8

The memory circuit according to Claim 5, in which said memory cells are of flip-flop type.

Claim 9

The memory circuit according to Claim 5, in which said second circuit includes a buffer circuit having an input terminal connected to said second terminal, a latch circuit, a transfer gate coupled between an input terminal of said latch circuit and an output terminal of said buffer circuit, means for operatively conducting said transfer gate in response to said second logic level of said first control signal, means for generating a second control signal which takes active level in response to said second logic level of said first control signal and changes to inactive level after said first control signal becomes said first logic level, and a data driver circuit having an input terminal coupled to an output terminal of said latch ci-cuit for generating an output as said held data.