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EP0094837A2
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Phase-locked circuit loop having improved locking capabilities
Assignee: Westinghouse Electric Corp
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Filing: 1983-05-17
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Granted: —
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Expires: 2003-05-17
Abstract
Abstract A phase-locked loop having improved off-frequency detection. A variable frequency output signal (V sw ) is to be precisely locked to the frequency and phase of an alternating input signal. This is accomplished by alternately utilizing two feedback loops [Fig. 1 (V out , 14, 15)). A reference signal (V ref 1 ,), having a frequency approximately equal to the frequency of the input signal is input to an initialization feedback loop 14 in which it is mixed with the output signal. The Initialization loop produces a feedback signal for controlling a voltage controlled oscillator (12) which generates the output signal. An off-frequency detector (32) detects the frequency difference between the output signal and the reference signal. When this frequency difference decreases below a predetermined level, the off-frequency detector disables the initialization feedback loop and enables a primary feedback loop. In the primary feedback loop the phase of the output signal is compared (14) to the phase of the input signal, and the difference signal controls the voltage controlled oscillator in such a manner that the phase of the output signal tracks the phase of the input signal. With this scheme, the initialization loop, which has a wide bandwidth, is used to control the voltage controlled oscillator over a wide range of frequencies of the output signal (i.e., the initialization loop has a broad capture range). When the frequency of the output signal has been brought within the capture range of the primary loop, operation is switched to the primary loop. The primary loop has a narrower bandwidth and therefore provides better noise rejection than the Initialization loop.
Inventors
- 👤 Ronald Lloyd Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 15:31
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/113
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
380 words
A phase-locked circuit loop having improved off-frequency detection for an alternating input signal ( V in ), comprising: oscillator means (12) providing an output signal (V out ) having a frequency and phase to be locked to the frequency and phase of said alternating input signal; phase detector means (14) for detecting a phase difference between said output and said input signals, and for producing a difference signal in response thereto, said phase detector means having a narrow bandwidth; switching means (34) selectively connecting said difference signal and said first mixed signal to said oscillator means for controlling the frequency and phase of said variable frequency output signal; means (Vrefl) providing a first reference signal; first mixer means (16) for mixing said output signal and said first reference signal and for producing a first mixed signal in response thereto; second mixer means (20) for mixing said delayed signal and said first reference signal and for producing a second mixed signal in response thereto; and characterized by: delay means (18) responsive to said first and said second mixed signals for imparting a phase difference between said first and said second mixed signals; logic means (40) responsive to said delay means for logically relating said first and said second mixed signals and for producing first (V L1 ) and second logic signals (V L2 ) in response thereto; flip-flop means (42) providing a flip-flop signal (V ff ) in response to said first and said second logic signals with the frequency of said flip-flop signal representing the difference between the frequency of said output signal and the frequency of said first reference signal; frequency detector means (43, 44) responsive to said flip-flop signal for producing an error signal representative of the frequency of said flip-flop signal; threshold detector means (46) responsive to said error signal for producing a switching signal, wherein said switching signal is in a first state when said error signal exceeds a predetermined value and in a second state when said predetermined value is not exceeded; said switching means responsive to said switching signal such that when said predetermined value is exceeded said first mixed signal is input to said oscillator means, and when said predetermined value is not exceeded said difference signal is input to said oscillator means.
Claim 2
Dependent Claim
380 words
A phase-locked circuit loop having improved off-frequency detection for an alternating input signal ( V in ), comprising: oscillator means (12) providing an output signal (V out ) having a frequency and phase to be locked to the frequency and phase of said alternating input signal; phase detector means (14) for detecting a phase difference between said output and said input signals, and for producing a difference signal in response thereto, said phase detector means having a narrow bandwidth; switching means (34) selectively connecting said difference signal and said first mixed signal to said oscillator means for controlling the frequency and phase of said variable frequency output signal; means (Vrefl) providing a first reference signal; first mixer means (16) for mixing said output signal and said first reference signal and for producing a first mixed signal in response thereto; second mixer means (20) for mixing said delayed signal and said first reference signal and for producing a second mixed signal in response thereto; and characterized by: delay means (18) responsive to said first and said second mixed signals for imparting a phase difference between said first and said second mixed signals; logic means (40) responsive to said delay means for logically relating said first and said second mixed signals and for producing first (V L1 ) and second logic signals (V L2 ) in response thereto; flip-flop means (42) providing a flip-flop signal (V ff ) in response to said first and said second logic signals with the frequency of said flip-flop signal representing the difference between the frequency of said output signal and the frequency of said first reference signal; frequency detector means (43, 44) responsive to said flip-flop signal for producing an error signal representative of the frequency of said flip-flop signal; threshold detector means (46) responsive to said error signal for producing a switching signal, wherein said switching signal is in a first state when said error signal exceeds a predetermined value and in a second state when said predetermined value is not exceeded; said switching means responsive to said switching signal such that when said predetermined value is exceeded said first mixed signal is input to said oscillator means, and when said predetermined value is not exceeded said difference signal is input to said oscillator means.
Claim 3
Dependent Claim
18 words
The phase-locked loop as claimed in claim 1 wherein the delay means includes an inverting buffer device (62).
Claim 4
Dependent Claim
56 words
The phase-locked loop as claimed in claim 1 or 2 wherein the first mixer means includes an EXCLUSIVE OR gate (64) having a first input terminal responsive to the output signal, a second input terminal responsive to the first reference signal, and an output terminal, and wherein the logic means is responsive to said output terminal.
Claim 5
Dependent Claim
54 words
The phase-locked loop as claimed in claim 1 wherein the second mixer means includes an EXCLUSIVE OR gate (66) having a first input terminal responsive to the output signal, a second input terminal responsive to the first reference signal, and an output terminal, and wherein the logic means is responsive to said output terminal.
Claim 6
Dependent Claim
98 words
The phase-locked loop as claimed in any one of claims 1 to 4 including: a second reference signal (V ref2 ) ' wherein the frequency of the first reference signal plus the frequency of said second reference signal is approximately equal to the frequency of the input signal; and third mixer means (22) disposed between the first mixer means and the logic means, for mixing said first mixed signal and said second reference signal and for producing a third mixed signal (V el ) in response thereto, wherein the logic means is responsive to said third mixed signal.
Claim 7
Dependent Claim
55 words
The phase-locked loop as claimed in claim 5 wherein the third mixer means includes an EXCLUSIVE OR gate (68) having a first input terminal responsive to the first mixed signal, a second input terminal responsive to the second reference signal, and an output terminal, and wherein the logic means is responsive to said output terminal.
Claim 8
Dependent Claim
60 words
The phase-locked loop as claimed in claim 5 or 6 including: fourth mixer means (24) disposed between the second mixer means and the logic means for mixing the second mixed signal and the second reference signal and for producing a fourth mixed signal (V e2 ) in response thereto, wherein the logic means is responsive to said fourth mixed signal.
Claim 9
Dependent Claim
55 words
The phase-locked loop as claimed in claim 7 wherein the fourth mixer means includes an EXCLUSIVE OR gate (70) having a first input terminal responsive to the second mixed signal, a second input terminal responsive to the second reference signal, and an output terminal, and wherein the logic means is responsive to said output terminal.
Claim 10
Dependent Claim
66 words
The phase-locked loop as claimed in claim 1 or 2 including first level detector means (36) disposed between the first mixer means and the logic means, said first level detector means responsive to the first mixed signal for transforming the first mixed signal to a first square wave signal (V s q l ), wherein the logic means is responsive to said first square wave signal.
Claim 11
Dependent Claim
65 words
The phase-locked loop as claimed in claim 1, 2 or 9 including second level detector means (38) disposed between the second mixer means and the logic means, said second level detector means responsive to the second mixed signal for transforming the second mixed signal to a second square wave signal (V sq2 ), wherein the logic means is responsive to said second square wave signal.
Claim 12
Dependent Claim
31 words
The phase-locked loop as claimed in claim 9 wherein the first level detector means includes first inverter means (88) responsive to the first mixed signal for producing a first inverted signal.
Claim 13
Dependent Claim
40 words
The phase-locked loop as claimed in claim 11 wherein the logic means includes first summing means (104, 106) for determining the logical sum of the first inverted signal and the second mixed signal and for producing the first logic signal.
Claim 14
Dependent Claim
31 words
The phase-locked loop as claimed in claim 10 wherein the second level detector means includes second inverter means (90) responsive to the second mixed signal for producing a second inverted signal.
Claim 15
Dependent Claim
40 words
The phase-locked loop as claimed in claim 16 wherein the logic means includes second summing means (108, 110) for determining the logical sum of the second inverted signal and the first mixed signal and for producing the second logic signal.
Claim 16
Dependent Claim
47 words
The phase-locked loop as claimed in claim 1, 2, 9 or 10 wherein the flip-flop means includes an S-R type flip-flop (116, 118) having an inverting set input terminal responsive to the first logic signal, and an inverting reset input terminal responsive to the second logic signal.
Claim 17
Dependent Claim
33 words
The phase-locked loop as claimed in claim 1 or 2 wherein the frequency detector means includes frequency-to-voltage converter means (43) for producing the error signal representative of the frequency of the flip-flop signal.
Claim 18
Dependent Claim
31 words
The phase-locked loop as claimed in claim wherein the frequency-to-voltage converter means includes integrating means (44) for integrating the flip- flip signal and for producing the error signal in response thereto.
Claim 19
Dependent Claim
32 words
The phase-locked loop as claimed in claim 1, 2, 14 or W wherein the threshold detector means includes a Schmitt trigger (46) responsive to the error signal for producing the switching signal.
Claim 20
Dependent Claim
28 words
The phase-locked loop as claimed in claim 1 or 2 wherein the frequency of the first reference signal is approximately equal to the frequency of the input signal.
Claim 21
Dependent Claim
36 words
The phase-locked loop as claimed in claim 1, 2 or 19 wherein the frequency of the first mixed signal is equal to the frequency of the output signal less the frequency of the first reference signal.
Claim 22
Dependent Claim
36 words
The phase-locked loop as claimed in claim 1, 2 or 19 wherein the frequency of the second mixed signal is equal to the frequency of the output signal less the frequency of the first reference signal.
References Cited (Backward Citations)
No citation records indexed.
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