EP0094177A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Apparatus for direct memory-to-memory intercomputer communication
Assignee: Digital Equipment Corp
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Filing: 1983-04-28
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Granted: —
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Expires: 2003-04-28
Abstract
Abstract Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other; the source and destination buffer names are contained right in the transmitted packet. The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed. For reading from the second node, the opcode actually causes the second node to write back to the first node; in this situation, the second node to write back to the first node; in this situation, che second node, upon detecting the appropriate opcode, places the remainder of the received packet on a command queue (202), to be excuted with the commands locally generated at the second node, without need for host interruption.
Inventors
- 👤 William D. Strecker
- 👤 Robert E. Stewart
- 👤 Samuel Fuller
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:30
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F15/177
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
271 words
Apparatus for transferring a block of information from a memory (24B) associated with a first node (14) of a data processing network to a memory (24C) associated with a second node (16) of the network, comprising: A. at the first node, a memory buffer (25A) adapted to be the source of the block of information for the transfer; B. at the second node, a memory buffer (25C) adapted to be the destination and to receive the block of information; C. each of the memory buffers (25A, 25C) being identified by a name established prior to the transfer and known to both nodes; D. bus means (18) for interconnecting the first and second nodes to permit communications therebetween; E. port means (26i) in each node for interconnecting a host computer or other device (22i, 24i) with the bus means (18); F. at the first node, means (32, 34, 46) for assembling the block of information into a sequence of at least one packet (37, 38, 39), the body of each packet including the name of the destination buffer (102) and the offset within it (104) where the block is to be placed and the last packet of the sequence being identified by a prearranged last packet flag; G. the port means (26B) of the first node being adapted to transmit said packet over the bus to the second node; H. at the second node, the port means (26C) being adapted to receive said packet from the bus; and I. the second node including means (208, 216, 204) for selectively writing a received packet to the destination memory buffer indicated in the packet.
Claim 2
Dependent Claim
271 words
Apparatus for transferring a block of information from a memory (24B) associated with a first node (14) of a data processing network to a memory (24C) associated with a second node (16) of the network, comprising: A. at the first node, a memory buffer (25A) adapted to be the source of the block of information for the transfer; B. at the second node, a memory buffer (25C) adapted to be the destination and to receive the block of information; C. each of the memory buffers (25A, 25C) being identified by a name established prior to the transfer and known to both nodes; D. bus means (18) for interconnecting the first and second nodes to permit communications therebetween; E. port means (26i) in each node for interconnecting a host computer or other device (22i, 24i) with the bus means (18); F. at the first node, means (32, 34, 46) for assembling the block of information into a sequence of at least one packet (37, 38, 39), the body of each packet including the name of the destination buffer (102) and the offset within it (104) where the block is to be placed and the last packet of the sequence being identified by a prearranged last packet flag; G. the port means (26B) of the first node being adapted to transmit said packet over the bus to the second node; H. at the second node, the port means (26C) being adapted to receive said packet from the bus; and I. the second node including means (208, 216, 204) for selectively writing a received packet to the destination memory buffer indicated in the packet.
Claim 3
Dependent Claim
56 words
The apparatus of claim 1 further including: J. at the second node, means (202) in the port means (26C) for sending to the first node a packet (110) confirming receipt of a sequence of related packets terminated by a packet having a last packet flag indicating that the packet is the last one in the sequence..
Claim 4
Dependent Claim
25 words
The apparatus of claim 2 wherein the first node is adapted to provide a response to its host responsive to receipt of said confirmation packet.
Claim 5
Dependent Claim
145 words
The apparatus of claim 1 or claim 2 further including: K. the means at the first node for assembling the packet being adapted to insert in each packet a packet type indication (i.e., opcode) (40A), such indication being selected from a plurality of previously designated packet type indications, including a first packet type indication signifying that the packet contains information for a destination memory buffer and a second type indication signifying that the packet contains a command to be executed at the second node; and L. at the second node, the means for selectively writing a received packet to the destination memory buffer including i. means (216) for decoding the packet type indication of each received packet, and ii. means (204) for directing the information contents of the packet to the indicated destination memory buffer responsive.to the packet type indication being of the first type.
Claim 6
Dependent Claim
25 words
The application of claim 4 the means for directing the information contents is responsive further to the presence or absence of the last packet flag.
Claim 7
Dependent Claim
36 words
The apparatus of claim 4 wherein the second node further includes: iii. means (202) for causing the command contents of the packet to be executed responsive to the packet type indication being of the second type.
Claim 8
Dependent Claim
44 words
The apparatus of claim 6 wherein for a packet of the second type, the command contents of the packet signify a write operation, whereby the first node can read from the second node by causing the second node to write to the first node.
Claim 9
Dependent Claim
40 words
The apparatus of claim 7 wherein the first node is adapted to provide a response to its host indication completion of reading from a second node upon receipt fo the last packet flag in the transmission from the seond node.
Claim 10
Dependent Claim
208 words
The apparatus of claim 1 or claim 2 further including: M. the means at the first node for assembling the packet being adapted to insert in each packet a packet type indication (i.e., opcode) (40A), such indication being selected from a plurality of previously designated packet type indications, including a first packet type -indication signifying that the packet contains information for a destination memory buffer and a second type indication signifying that the packet contains a command to be executed at the second node; and N. at the second node, the means for selectively writing a received packet to the destination memory buffer including i. a response queue (204) for temporarily storing in queue entries, information to be subsequently sent from the port to the host; ii. a command queue (202) for temporarily storing commands to be executed; iii. a free queue (208) for maintaining queue entries available for use by the response queue and the command queue; iv. means (216) for decoding the packet type indication of a receive packet for directing the packet to the memory buffer responsive to the packet type indication being of the first type or to the response queue responsive to the packet type indication being of being of the second type.
Claim 11
Dependent Claim
268 words
Apparatus for transferring a block of information from a memory (24B) associated with a first Port (26B) of a data processing network to a memory (24C) associated with a second port (26C) of the network, comprising: A. in the memory (24B) associated with the first node, a memory buffer (25A) adapted to be the source of the block of information for the transfer; B. in the memory (24C) associated with the second node, a memory buffer (25C) adapted to be the destination and to receive the block of information; C. each of the memory buffers (25A, 25C) being identified by a name established prior to the transfer and known to both ports D. bus means (18) for interconnecting the first and second ports to permit communications therebetween; E. each port being adapted to interconnect a host computer (22i, 24i) with the bus means (18); F. the first port including means (32, 34, 46) for assembling the block of information into a sequence of at least one packet (37, 38, 39), the body of each packet including the name of the destination buffer (102) and the offset within it (104) where the block is to be placed and the last packet of the sequence being identified by a prearranged last packet flag; G. the first port (26B) being adapted to transmit said packet over the bus to the second port; H. the second port (26C) being adapted to receive said packet from the bus; and I. the second port including means (208, 216, 204) for selectively writing a received packet to the destination memory buffer indicated in the packet.
Claim 12
Dependent Claim
268 words
Apparatus for transferring a block of information from a memory (24B) associated with a first Port (26B) of a data processing network to a memory (24C) associated with a second port (26C) of the network, comprising: A. in the memory (24B) associated with the first node, a memory buffer (25A) adapted to be the source of the block of information for the transfer; B. in the memory (24C) associated with the second node, a memory buffer (25C) adapted to be the destination and to receive the block of information; C. each of the memory buffers (25A, 25C) being identified by a name established prior to the transfer and known to both ports D. bus means (18) for interconnecting the first and second ports to permit communications therebetween; E. each port being adapted to interconnect a host computer (22i, 24i) with the bus means (18); F. the first port including means (32, 34, 46) for assembling the block of information into a sequence of at least one packet (37, 38, 39), the body of each packet including the name of the destination buffer (102) and the offset within it (104) where the block is to be placed and the last packet of the sequence being identified by a prearranged last packet flag; G. the first port (26B) being adapted to transmit said packet over the bus to the second port; H. the second port (26C) being adapted to receive said packet from the bus; and I. the second port including means (208, 216, 204) for selectively writing a received packet to the destination memory buffer indicated in the packet.
Claim 13
Dependent Claim
180 words
Apparatus (26i) for interconnecting a computer (22i, 24i) or other device, termed the host, with a communications bus (18) for use in building a network of hosts adapted to communicate with one another via the bus, such apparatus being termed a port, each host (e.g., 22B, 24B) including a memory device (24B) having at least one memory buffer (25A) adapted to serve as the source of a block of information to be transferred over the bus and at least one memory buffer (e.g., 25A) adapted to serve as the destination of a block of information sent over the bus to that host, said memory buffers being named, the apparatus comprising: means for assembling a block of information ' supplied by the host into a sequence of at least one packet (37, 38, 39), the body of each packet including the name of the destination buffer (102) for the transfer, the offset (104) for the address within the destination buffer where the packet is to be writing; and means for transmitting said sequence of at least one packet onto the bus.
Claim 14
Dependent Claim
180 words
Apparatus (26i) for interconnecting a computer (22i, 24i) or other device, termed the host, with a communications bus (18) for use in building a network of hosts adapted to communicate with one another via the bus, such apparatus being termed a port, each host (e.g., 22B, 24B) including a memory device (24B) having at least one memory buffer (25A) adapted to serve as the source of a block of information to be transferred over the bus and at least one memory buffer (e.g., 25A) adapted to serve as the destination of a block of information sent over the bus to that host, said memory buffers being named, the apparatus comprising: means for assembling a block of information ' supplied by the host into a sequence of at least one packet (37, 38, 39), the body of each packet including the name of the destination buffer (102) for the transfer, the offset (104) for the address within the destination buffer where the packet is to be writing; and means for transmitting said sequence of at least one packet onto the bus.
Claim 15
Dependent Claim
58 words
The apparatus of claim 11 further including: means for receiving signals transmitted on the bus and means for sending over the bus, to an originating node, a packet (110) confirming correct receipt of a sequence of related packets terminated by a packet having a last packet flag indicating that the packet is the last one in the sequence.
Claim 16
Dependent Claim
76 words
The apparatus of claim 11 or claim 12 further including: the means for assembling including means for inserting in each packet a packet type indication (i.e., opcode) (40A), such indication being selected from a plurality of previously designated packet type indications, including a first packet type indication signifying that the packet contains information for a destination memory buffer and a second type indication signifying that the packet contains a command to be executed at another port.
References Cited (Backward Citations)
No citation records indexed.
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