EP0093267A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for switching the control of central processing units in a data processing system, and apparatus for initiating the switching of CPU control
Assignee: International Business Machines Corp
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Filing: 1983-03-30
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Granted: —
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Expires: 2003-03-30
Abstract
Abstract A method is disclosed which improves, in a uniprocessor or multiprocessor system, the switching of CPU control between different system control programs SCP. An interface area PSA (42(0), 43(0)...42(n), 43(n)) for storing old and new program status words is provided in common main storage separately for each SCP and CPU. Switching from one SCP to another for any CPU is effected by changing the contents of a prefix register (21) in the respective CPU. This switching is not controllable by user instructions executed on the CPU. The method enables a preferred guest SCP (such as MVS/370) to operate in a system having a particular host SCP (such as VM/370) with an efficiency that is almost the same as if the preferred guest were operating as a standalone SCP on its own dedicated system. Also disclosed is apparatus for initiating the switching of CPU control between different SCPs.
Inventors
- 👤 George Henry Bean
- 👤 Peter Hermon Gum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 21:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/44; G06F9/455; G06F9/45533
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
352 words
A method of switching the control of any central processing unit CPU in a multiprocessor or uniprocessor data processing system among a plurality of system control programs, a next instruction to be executed by the CPU being located by an instruction address in a program status word register (22) in the CPU, the CPU requiring a hardware-to-software interface area (42) in main storage (40) of the system for storing old and new program status word values, characterized in that a separate hardware-to-software interface area (42, 43) is provided for each system control program which is to control the respective CPU, the contents of a prefix register (21) in the CPU identifying the main storage location of the interface area of a currently selected system control program, and further characterized by the steps of sensing an event occuring in, or signalled to, the CPU that requires CPU operation under control of a particular system control program, identifying the system control program currently controlling the CPU, determining whether the current system control program is the required system control program to control the CPU when the CPU handles the event sensed by the sensing step, loading the prefix register in the CPU with an address for locating the interface area of the particular system control program required to control handling of the sensed event if the determining step indicates that the current system control program is not the required system control program, and- interrupting the CPU operation, if the loading step is executed, by storing a value from the program status word register into, and by loading the program status word register with a new program status word value from, fields associated with the sensed event in the interface area located by the address in the prefix register after being loaded by the loading step, whereby the loading step effects a CPU control switching for changing the control of the CPU from a given system control program controlling the CPU at the time of occurence of the event to the particular system control program which is to control the CPU for responding to the event.
Claim 2
Independent Claim
352 words
A method of switching the control of any central processing unit CPU in a multiprocessor or uniprocessor data processing system among a plurality of system control programs, a next instruction to be executed by the CPU being located by an instruction address in a program status word register (22) in the CPU, the CPU requiring a hardware-to-software interface area (42) in main storage (40) of the system for storing old and new program status word values, characterized in that a separate hardware-to-software interface area (42, 43) is provided for each system control program which is to control the respective CPU, the contents of a prefix register (21) in the CPU identifying the main storage location of the interface area of a currently selected system control program, and further characterized by the steps of sensing an event occuring in, or signalled to, the CPU that requires CPU operation under control of a particular system control program, identifying the system control program currently controlling the CPU, determining whether the current system control program is the required system control program to control the CPU when the CPU handles the event sensed by the sensing step, loading the prefix register in the CPU with an address for locating the interface area of the particular system control program required to control handling of the sensed event if the determining step indicates that the current system control program is not the required system control program, and- interrupting the CPU operation, if the loading step is executed, by storing a value from the program status word register into, and by loading the program status word register with a new program status word value from, fields associated with the sensed event in the interface area located by the address in the prefix register after being loaded by the loading step, whereby the loading step effects a CPU control switching for changing the control of the CPU from a given system control program controlling the CPU at the time of occurence of the event to the particular system control program which is to control the CPU for responding to the event.
Claim 3
Dependent Claim
161 words
A CPU control switching method as defined in claim 1, the sensed event being an external signal from another CPU to a local CPU, characterized in that the determining step comprises detecting the state of an enabling mask field which controls the handling by a specific system control program of a CPU external interruption requested by the external signal, one state of the enabling mask field enabling the specific system control program to handle a CPU external interruption, and the other state of the enabling mask field indicating that' the specific system control program should not handle a CPU external interruption, and that the loading step is effected if the specific system control program is in control of the CPU and the other state exists in the enabling mask field so that a CPU control switching is done by the loading step to put the particular system control program in control of the CPU before a CPU external interruption is started.
Claim 4
Dependent Claim
162 words
A CPU control switching method as defined in claim 1, the sensed event being an I/O instruction, characterized in that the determining step comprises detecting the state of a field in a dedication mask entry, the field corresponding to a set of I/O devices connected to the CPU, one state of the field indicating that the set of I/O devices is dedicated to a specific system control program, and the other state of the field indicating that the set of I/O devices is not dedicated to the specific system control program, and that the loading step is effected if the dedication mask field is in the other state and the specific system control program is in control of the CPU when an I/O instruction is about to be executed, so that a CPU control switching is done by the loading step to put the particular system control program in control of the CPU before the I/O instruction is executed by the CPU.
Claim 5
Dependent Claim
164 words
A CPU control switching method as defined in claim 1, the sensed event being an I/O interruption for which the CPU is enabled, characterized in that the determining step comprises detecting the state of a field in a dedication mask entry, the field corresponding to a set of I/O devices connected to the CPU, one state of the field indicating that the set of I/O devices is dedicated to a specific system control program, and the other state of the field indicating that the set of I/O devices is not dedicated to the specific system control program, and that the loading step is effected if the specific system control program is in control of the CPU when an I/O interruption is to be taken by the CPU for the respective set of I/O devices, so that a CPU control switching is done by the loading step to put the particular system control program in control of the CPU before the I/O interruption is started.
Claim 6
Dependent Claim
69 words
A CPU control switching method as defined in claim 1, characterized in that a system control program indicating field in a control register is loaded to indicate the current system control program being in control of the CPU, after loading the prefix register with an address, and that the identifying step uses the system control program indicating field to determine which system control program is currently controlling the CPU.
Claim 7
Dependent Claim
90 words
A CPU control switching method as defined in claim 1, further characterized by providing a control register in the CPU with a main storage address of a control block containing a particular interface area pointer for the particular system control program, fetching the particular interface area pointer using the address in the control register when the identifying step indicates that the particular system control program is not controlling the CPU, and storing, in the loading step, the particular interface area pointer obtained by the fetching step into the prefix register.
Claim 8
Dependent Claim
213 words
A CPU control switching method as defined in claim 6, the sensed event being an I/O interrupt signal from an I/O channel received while the CPU is enabled for I/O interruption, further characterized by initially loading a channel dedication mask into a channel dedication mask register in the CPU, positions of dedication mask fields in the register corresponding to respective I/O channels, the state of each respective field position indicating whether the corresponding I/O channel is dedicated to a specific system control program or not, detecting the state of the field in the channel dedication mask register corresponding to the I/O channel sending the I/O interrupt signal to determine whether or not the I/O channel is dedicated to the specific system control program, the loading step being executed if it is detected that the I/O channel is not dedicated to the specific system control program and the specific system control program is in control of the CPU, but the loading step being not executed if it is detected that the specific system control program is in control of the CPU and the I/O channel is dedicated to the specific system control program, so that the specific system control program handles the I/O interrupt from the dedicated I/O channel without switching of CPU control.
Claim 9
Dependent Claim
159 words
A CPU control switching method as defined in claim 1, the sensing step indicating that the event is the execution by the CPU of a special system control instruction, further characterized by effecting the loading step if the CPU is in supervisor state while the identifying step indicates that the particular system control program is not in control of the CPU, but not effecting the loading step if either the CPU is in problem state or the identifying step indicates that the particular system control program is in control of the CPU, and suppressing the CPU execution of the special system control instruction and interrupting the CPU with a program interrupt if the loading step has been executed, whereby the interface area of the particular system control program is used in executing the program interrupt of the CPU, and whereby the particular system control program can thereafter determine whether to execute the function of the special system control instruction.
Claim 10
Dependent Claim
208 words
A CPU control switching method as defined in claim 1, the sensing step indicating that the event is the execution by the CPU of an I/O control instruction and indicating which device is selected for the I/O control instruction, further characterized by effecting the loading step if an I/O device set dedication mask field indicates that the I/O device set associated with the selected device is not dedicated to the given system control program while the CPU is in supervisor state and the identifying step indicates that the particular system control program is not in control of the CPU, but not effecting the loading step if either the mask field indicates that the device is dedicated to the given system control program or the CPU is in problem state while the identifying step indicates that the particular system control program is not in control of the CPU, suppressing the execution of the I/O control instruction and interrupting the CPU with a program interrupt if the loading step has been executed, whereby the interface area of the particular system control program is used in executing the program interrupt of the CPU and whereby the particular system control program can thereafter determine whether to execute a replacement I/O control instruction.
Claim 11
Dependent Claim
309 words
Apparatus for initiating the switching of control of a central processing unit CPU in a multiprocessor or uniprocessor data processing system from a preferred guest system control program to a host system control program, a next instruction to be executed by the CPU being located by an instruction address in a program status word register (22) in the CPU; each system control program having a hardware-to-software interface area (42, 43) for the respective CPU in a main storage of the system for storing old and new program status word values; the CPU containing an interval timer for generating timer interrupt signals; the program status word register containing bit positions for an I/O mask, external mask, CPU wait state, and CPU supervisor state; and a first control register (CR2) containing I/O channel-enablement bit positions respectively corresponding to I/O channel numbers architected for the system; characterized in that it comprises: a preferred-guest-indicating bit position (PG) in a second control register (CR6) in the CPU in which a first state indicates that the preferred guest system control program is in control and a second state indicates that the host system control program is in control of the CPU, a preferred guest mask latch (45) in the CPU which is set to a first state when the preferred guest system control program is enabled to handle external interrupts and is set to a second state when the preferred guest system control program is not enabled to handle external interrupts, and first AND circuitry (66) for receiving a CPU enabled external interrupt signal from another CPU, the output of the preferred guest mask latch, and a signal representing the state of the preferred-guest-indicating bit position, the output signal from the first AND circuitry constituting a control signal for initiating CPU control switching from the guest system control program to the host system control program.
Claim 12
Dependent Claim
309 words
Apparatus for initiating the switching of control of a central processing unit CPU in a multiprocessor or uniprocessor data processing system from a preferred guest system control program to a host system control program, a next instruction to be executed by the CPU being located by an instruction address in a program status word register (22) in the CPU; each system control program having a hardware-to-software interface area (42, 43) for the respective CPU in a main storage of the system for storing old and new program status word values; the CPU containing an interval timer for generating timer interrupt signals; the program status word register containing bit positions for an I/O mask, external mask, CPU wait state, and CPU supervisor state; and a first control register (CR2) containing I/O channel-enablement bit positions respectively corresponding to I/O channel numbers architected for the system; characterized in that it comprises: a preferred-guest-indicating bit position (PG) in a second control register (CR6) in the CPU in which a first state indicates that the preferred guest system control program is in control and a second state indicates that the host system control program is in control of the CPU, a preferred guest mask latch (45) in the CPU which is set to a first state when the preferred guest system control program is enabled to handle external interrupts and is set to a second state when the preferred guest system control program is not enabled to handle external interrupts, and first AND circuitry (66) for receiving a CPU enabled external interrupt signal from another CPU, the output of the preferred guest mask latch, and a signal representing the state of the preferred-guest-indicating bit position, the output signal from the first AND circuitry constituting a control signal for initiating CPU control switching from the guest system control program to the host system control program.
Claim 13
Dependent Claim
67 words
Control switching initiation apparatus as defined in claim 10, characterized in that it further comprises: second AND circuitry (67) for receiving a CPU enabled timer interrupt signal and a signal representing the state of the preferred-guest-indicating bit position, the output signal from the second AND circuitry constituting a control signal for initiating CPU control switching from the guest system control program to the host system control program.
Claim 14
Dependent Claim
169 words
Control switching initiation apparatus as defined in claim 10, characterized in that it further comprises: a channel dedication mask register (23) including preferred guest channel dedication mask bit positions corresponding to I/O channel numbers architected for the system, a first state of any channel dedication mask bit position indicating that the preferred guest system control program is enabled to handle I/O interrupt requests from the corresponding I/O channel and a second state of the bit position indicating that the preferred guest system control program is not enabled to handle I/O interrupt requests from the corresponding I/O channel, and third AND circuitry (71, 72, 73) for receiving a CPU enabled I/O interrupt signal from an I/O channel, a signal representing the state of the preferred-guest-indicating bit position, and a signal representing the state of the corresponding channel dedication mask bit position, the output signal from the third AND circuitry constituting a control signal for initiating CPU control switching from the guest system control program to the host system control program.
Claim 15
Dependent Claim
226 words
Control switching initiation apparatus as defined in claim 10, characterized in that it further comprises: a channel dedication mask register (23) with preferred guest channel dedication mask bit positions corresponding to I/O channel numbers architected for the system, a first state of any channel dedication mask bit position indicating that the preferred guest system control program is enabled to control the execution of I/O instructions for the corresponding channel and a second state of the bit position indicating that the preferred guest system control program is not enabled to control the execution of I/O instructions for the corresponding channel, instruction unit signalling means (81) for signalling the execution of an I/O instruction for a selected channel while the CPU is in privileged state, fourth AND circuitry (80, 82, 87) for receiving a signal from the instruction unit signalling means indicating pre-execution of an I/O instruction for a selected I/O channel, a signal representing the state of the preferred-guest-indicating bit position, and a signal representing the state of the corresponding channel dedication mask bit position, and means (95, 96) for suppressing the CPU execution of the I/O instruction in response to an output from the fourth AND circuitry, the output signal from the fourth AND circuitry constituting a control signal for initiating CPU control switching from the guest system control program to the host system control program.
Claim 16
Dependent Claim
114 words
Control switching initiation apparatus as defined in claim 10, characterized in that it further comprises: instruction unit signalling means (93) for signalling the execution of a system-control instruction while the CPU is in a privileged state, fifth AND circuitry (83, 88) for receiving a signal from the instruction unit signalling means and a signal representing the state of the preferred-guest-indicating bit position, and means (95, 96) for suppressing the CPU execution of the system-control instruction in response to an output from the fifth AND circuitry, the output signal from the fifth AND circuitry constituting a control signal for initiating CPU control switching from the guest system control program to the host system control program.
Claim 17
Dependent Claim
75 words
Control switching initiation apparatus as defined in claim 10, characterized in that it further comprises: sixth AND circuitry (86) for receiving a signal representing the CPU wait state from the program status word register (22) and a signal representing the state of the preferred-guest-indicating bit position, the output signal from the sixth AND circuitry constituting a control signal for initiating CPU control switching from the guest system control program to the host system control program.
References Cited (Backward Citations)
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