Circuit and method for generating a ramp signal

Claim 2

A circuit for generating a ramp signal, comprising means (90) for providing in response to a D.C. input step signal an integrated D.C. ramp voltage; means (11) for limiting said D.C. ramp voltage; means (77,78) for detecting in succession predetermined magnitudes obtained by said D.C. ramp voltage; and means (71,73,72,74) for successively increasing or decreasing the slope of said ramp voltage, according as the ramp voltage is increasing or decreasing respectively, in response to detected predetermined magnitudes obtained by said ramp voltage.

Claim 3

A circuit according to claim 1 wherein said means for successively increasing or decreasing the slope of said ramp voltage comprises means for changing said time constant.

Claim 4

A circuit according to claim 1 or claim 2 wherein said means for limiting is adjustable.

Claim 5

A circuit for generating a bias or erase signal for application to a magnetic head (34) of a video tape machine and including means for generating a ramp signal and means (28) for chopping the ramp signal at a desired signal frequency to provide the bias or erase signal, characterised by the combination of means (40) for providing in response to a D.C. input step signal an integrated D.C. ramp voltage; means (11) for limiting said D.C. ramp voltage; means (77,78) for detecting in succession predetermined magnitudes obtained by said D.C. ramp voltage; and means (71-74)for successively increasing or decreasing in stages the slope of said ramp voltage, according as the ramp voltage is increasing or decreasing respectively, in response to detected predetermined magnitudes attained by said ramp voltage.

Claim 6

A circuit for generating a bias or erase signal for application to a magnetic head (34) of a video tape machine and including means for generating a ramp signal and means (28) for chopping the ramp signal at a desired signal frequency to provide the bias or erase signal, characterised by the combination of means (40) for providing in response to a D.C. input step signal an integrated D.C. ramp voltage; means (11) for limiting said D.C. ramp voltage; means (77,78) for detecting in succession predetermined magnitudes obtained by said D.C. ramp voltage; and means (71-74)for successively increasing or decreasing in stages the slope of said ramp voltage, according as the ramp voltage is increasing or decreasing respectively, in response to detected predetermined magnitudes attained by said ramp voltage.

Claim 7

A circuit according to claim 1 or claim 4 wherein the means for providing an integrated ramp voltage comprises an integrating amplifier having input (21) coupled to receive a positive or negative D.C. input step voltage for responsively coupling said inverting input to a reference voltage or ground, respectively, having a non-inverting input (20) coupled to receive a-predetermined ratio of said reference voltage and having an output coupled to provide said ramp signal in response to said D.C. input step voltage; said integrating means is coupled to receive said reference voltage and to limit a maximum value of said ramp signal provided thereby to a value determined by said reference voltage; said integrating means has a series input resistor (23) coupled between an input terminal for receiving said input step voltage and said inverting input and a feedback capacitor (26) coupled between said output and said inverting input of said integrating means and has a plurality of further input resistors (71,72) and associated switches (73,74) each further input resistor being coupled in parallel to said series input resistor via a respective switch; and the detecting means is responsive to a predetermined magnitude of said ramp signal to apply a respective control signal to activate a respective switch (73,74).

Claim 8

A circuit according to claim 5 wherein said integrating means has a time constant determined by said series input resistor and capacitor and wherein for an increasing ramp signal said switches (73,74) are controlled in a first succession to decrease said time constant and for a decreasing ramp signal said switches are controlled in a second succession opposite to said first succession to increase said time constant.

Claim 9

A circuit according to claim 6 wherein for said increasing ramp signal said switches (73,74) are controlled to connect in said first succession said respective further resistors to said series input resistor and for said decreasing ramp signal said switches are controlled to disconnect in said second succession said respective further resistors from said series input resistor.

Claim 10

A circuit according to any of claims 5 to 7 further comprising a first resistive voltage divider (15,16) having one terminal coupled to said reference voltage, having a second, opposite terminal grounded and having an output terminal (18) provided between said first and second terminal, respectively, said output terminal being coupled to said non-inverting input of the integrating means.

Claim 11

A circuit according to claim 8 wherein respective resistance values between said first and said output terminal and between said second and said output terminal of said resistive voltage divider means are equal to obtain a time interval necessary for ramping-up equal to that which is necessary for ramping-down said ramp signal.

Claim 12

A circuit according to any foregoing claim wherein said detecting means (77,78) comprises means for comparing voltage levels obtained by said ramp signal with respective predetermined D.C. voltage reference values each obtained as a respective predetermined ratio of a first reference voltage.

Claim 13

A circuit according to claim 10 wherein said detecting means comprises a plurality of voltage comparators and voltage divider means (85,86,87,88), each voltage comparator having a first non-inverting input coupled to said output of said integrating means and a second inverting input coupled to an output of said voltage divider means, respectively, each said voltage divider means having a first terminal coupled to an output of said source for providing said first D.C. reference voltage and having a second, opposite terminal grounded, and wherein an output of each said voltage comparator is coupled to a control input of one of said switch means.

Claim 16

A method according to claim 12 wherein said step of successively increasing or decreasing the slope of said ramp voltage, respectively, is provided by successively decreasing or increasing said selected integrating time constant, respectively in predetermined increments.

Claim 17

A method according to claim 12 or claim 13 wherein said D.C. reference voltage is adjustable.