Method of forming emitter and intrinsic base regions of a bipolar transistor

Claim 2

Method of forming the emitter and base regions (44, 42) of an NPN bipolar transistor comprising: depositing a polycrystalline silicon layer (30) over a monocrystalline silicon surface in which the base and emitter regions (42, 44) of said transistor are to be formed; ion implanting boron ions (32) into polycrystalline silicon layer (30) near the interface of polycrystalline silicon layer (30) with said monocrystalline silicon; first annealing the layered structure to partially drive the boron ions (32) into said monocrystalline silicon (14) ; ion implanting arsenic ions (38) into polycrystalline silicon layer (30); and second annealing the layered structure to fully drive in the boron (32) and arsenic (38) to form base and emitter regions (42, 44) of said transistor.

Claim 3

Method of claim 1 wherein base region (36, 42) is the intrinsic base region of said NPN transistor and said extrinsic base region (28) is formed by another process to be contiguous with intrinsic base region (42).

Claim 4

Method of claim 2 wherein extrinsic base region (28) is formed from an outdiffusion from doped polycrystalline silicon layer (24) which remains in the final structure as the contact to intrinsic base region (42).

Claim 5

Method of claim 1 wherein polycrystalline silicon layer (30) remains in the final structure as the contact to emitter region (44).

Claim 6

Method of claim 1 wherein the thickness of polycrystalline silicon layer (30) is between 50 to 500 nanometers.

Claim 7

Method of claim 5 wherein the ion implanting of boron ions (32) use between about 5 to 30 KeV and ion implanting of arsenic ions (38) use between about 5 to 40 KeV.

Claim 8

Method of claim 1 wherein the first annealing is at a temperature between 800°C to 1000°C and second annealing is at a temperature between 850°C to 1000°C.

Claim 9

Method of claim 7 wherein first and second annealing are done in a nitrogen ambient.

Claim 10

Method of claim 1 wherein a silicon dioxide capping layer (34) is formed over polycrystalline silicon layer (30) after ion implanting boron ions (32) and before said first annealing, and removing capping layer (34) after said first annealing.

Claim 11

Method of claim 1 wherein polycrystalline silicon layer (30) has a doping level of between 5 x 1 0 18 to 5 x 10 19 boron atoms/cc, and between 5 x 10 19 to 2 x 10 21 arsenic atoms/cc.

Claim 12

Method of claim 10 wherein the resulting PN base-emitter junction is between 20 to 200 nanometers in depth.

Claim 13

Method of forming NPN transistors-in an integrated circuit comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions (18, 20); providing a mask layer (22) over said body covering that region designated to be the collector reach-through region and open to those designated as emitter, intrinsic base and extrinsic base regions (44; 36, 42; 28); forming a first P type doped polycrystalline silicon layer (24) over the surface of said body wherein the said polycrystalline silicon layer makes ohmic contact to extrinsic base region (28); removing polycrystalline silicon layer (24) from over mask layer (22) where said collector reach-through region is made; forming an insulating layer (26) over said surface and using lithography removing insulating layer (26) and polycrystalline silicon layer (24) from said regions where regions designated to be the emitter (44) and intrinsic base (36, 42) are to be made; forming an insulating layer over said surface; removing said insulating layer from over said surface to form a sidewall on the sides of first P type doped layer (24) defined by the region designated to be the emitter (44) and intrinsic base (42); forming a second polycrystalline silicon layer (30) over said regions in said body designated to be the emitter (44) and intrinsic base (36, 42); ion implanting boron ions (32) into second polycrystalline silicon layer (30) near the interface of polycrystalline silicon layer (30) with monocrystalline silicon body (14); first annealing the layered structure to partially drive in the boron (32) and the P type impurities from first P doped layer (24) and second polycrystalline silicon layer (30) into said monocrystalline silicon body; ion implanting arsenic ions (38) into second polycrystalline silicon layer (30); second annealing the layered structure to fully drive in the boron P type impurity (32) and arsenic (38) into the appropriately designated regions to form the intrinsic base (42), extrinsic base (28) and emitter (44) of said NPN transistors; and making electrical contact (50, 52) to the elements of said NPN transistor.

Claim 14

Method of forming NPN transistors-in an integrated circuit comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions (18, 20); providing a mask layer (22) over said body covering that region designated to be the collector reach-through region and open to those designated as emitter, intrinsic base and extrinsic base regions (44; 36, 42; 28); forming a first P type doped polycrystalline silicon layer (24) over the surface of said body wherein the said polycrystalline silicon layer makes ohmic contact to extrinsic base region (28); removing polycrystalline silicon layer (24) from over mask layer (22) where said collector reach-through region is made; forming an insulating layer (26) over said surface and using lithography removing insulating layer (26) and polycrystalline silicon layer (24) from said regions where regions designated to be the emitter (44) and intrinsic base (36, 42) are to be made; forming an insulating layer over said surface; removing said insulating layer from over said surface to form a sidewall on the sides of first P type doped layer (24) defined by the region designated to be the emitter (44) and intrinsic base (42); forming a second polycrystalline silicon layer (30) over said regions in said body designated to be the emitter (44) and intrinsic base (36, 42); ion implanting boron ions (32) into second polycrystalline silicon layer (30) near the interface of polycrystalline silicon layer (30) with monocrystalline silicon body (14); first annealing the layered structure to partially drive in the boron (32) and the P type impurities from first P doped layer (24) and second polycrystalline silicon layer (30) into said monocrystalline silicon body; ion implanting arsenic ions (38) into second polycrystalline silicon layer (30); second annealing the layered structure to fully drive in the boron P type impurity (32) and arsenic (38) into the appropriately designated regions to form the intrinsic base (42), extrinsic base (28) and emitter (44) of said NPN transistors; and making electrical contact (50, 52) to the elements of said NPN transistor.

Claim 15

Method of claim 12 wherein first P type doped polycrystalline silicon layer (24) is doped with boron impurities at a doping level of between 1 x 10 18 to 1 x 10 21 atoms/cc.

Claim 16

Method of claim 13 wherein first polycrystalline silicon layer (24) remains in the final integrated circuit structure as the electrical contact (50) to base region (42) and second polycrystalline silicon layer (30) remains in the final integrated circuit structure as the electrical contact (52) to emitter region (44).