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EP0090543A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Differential amplifier with improved linear amplification

Assignee: Fujitsu Ltd
•
Filing: 1983-03-15
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Granted: —
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Expires: 2003-03-15
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Abstract

Abstract A differential amplifier essentially comprises first and second transistors (Q 1 , Q 2 ) each having a negative resistance feedback. A current source (IP 2 ) and a third transistor (Q 3 ) connected in series are provided on the side of the first transistor (Q,), and a current source (IP 3 ) and a fourth transistor (Q 4 ) connected in series are provided on the side of the transistor (Q 2 ). The base end emitter of the first transistor (Q,) are connected respectively to the collector and base of the third transistor (Q 3 ) so that the potential at the base of the first transistor is negatively fed back to the emitter thereof. Similarly, the base and emitter of the second transistor (Q 2 ) are connected respectively to the collector and base of the fourth transistor (Q 4 ) so that the potential at the base of the second transistor is negatively fed back to the emitter thereof.

Inventors

  • 👤 Yoshiaki Sano

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 00:39
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3211

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 197 words
A differential amplifier comprising a primarycur- rent source (IP 1 ) for producing a first current (2I EE ) ; first and second transistors (Q , Q ) having a first polarity, each of the transistors having a collector serving as an output terminal, a base, and an emitter connected, via an emitter resistance (R E ), to the primary current source; characterized by first and second current sources (IP 2 , IP 3 ) for producing a second current (I BB ), the bases of the first and second transistors (Q 1 , Q 2 ) being connected to the first and second current sources respectively; a third transistor (Q 3 ) having a collector connected to the first current source (IP 2 ), a base connected to the emitter of the first transistor (Q 1 ), and an emitter for receiving a first input signal (ΔV in ); and a fourth transistor (Q4) having the first polarity, the fourth transistor having a collector connected to the second current source (IP3), a base connected to the emitter of the second transistor (Q 2 ), and an emitter for receiving a second input signal (V 1 ).
Claim 2
Dependent Claim 197 words
A differential amplifier comprising a primarycur- rent source (IP 1 ) for producing a first current (2I EE ) ; first and second transistors (Q , Q ) having a first polarity, each of the transistors having a collector serving as an output terminal, a base, and an emitter connected, via an emitter resistance (R E ), to the primary current source; characterized by first and second current sources (IP 2 , IP 3 ) for producing a second current (I BB ), the bases of the first and second transistors (Q 1 , Q 2 ) being connected to the first and second current sources respectively; a third transistor (Q 3 ) having a collector connected to the first current source (IP 2 ), a base connected to the emitter of the first transistor (Q 1 ), and an emitter for receiving a first input signal (ΔV in ); and a fourth transistor (Q4) having the first polarity, the fourth transistor having a collector connected to the second current source (IP3), a base connected to the emitter of the second transistor (Q 2 ), and an emitter for receiving a second input signal (V 1 ).
Claim 3
Dependent Claim 82 words
A differential amplifier according to claim 1, wherein the primary current source (IP 1 ) comprises third and fourth current sources (IP 1 ', IP 1 ") for producing the first current (IEE), the emitters of the first and second transistors (Q 1 , Q 2 ) being connected to the third and fourth current sources, respectively; and wherein the emitters of the first and second transistors (Q 1' Q 2 ) are connected to a common emitter resistance (R E ').
Claim 4
Dependent Claim 98 words
A differential amplifier according to claim 1 or claim 2, further comprising a fifth transistor (Q 5 ) having a second polarity opposite to the first polarity, the fifth transistor having an emitter connected to the emitter of the third transistor (Q3), a base for receiving the first input signal (ΔV in ), and a collector; and a sixth transistor (Q 6 ) having the second polarity, the sixth transistor having an emitter connected to the emitter of the fourth transistor (Q 4 ), a base for receiving the second input signal (V in ), and a collector.

References Cited (Backward Citations)

DE2204419B2 Cited
DE2846940A1 Cited
DE3035471A1 Cited
DE3138078A1 Cited

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