EP0090280A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device and method of making the same
Assignee: Nissan Motor Co Ltd
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Filing: 1983-03-17
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Granted: —
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Expires: 2003-03-17
Abstract
Abstract In a semiconductor integrated circuit device, a vertical type MOS FET is formed in a semiconductor substrate in such a manner that the semiconductor substrate constitutes the drain region thereof, the vertical type MOS FET being connected to a load for switching on and off a current flowing through the load; a first lateral type MOS FET is formed in the drain region of the vertical type MOS FET and connected to protect the latter from an excessive current which tends to flow when the load is shortcircuited; and a second lateral type MOS FET is also formed in the drain region of the vertical type MOS FET and used as an element in a detection-control circuit for controlling the first lateral type MOS FET by detecting the shirt-circuit of the load.
Inventors
- 👤 Teruyoshi Mihara
- 👤 Koichi Nissan-Uragou-Ryou Murakami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 05:33
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/082; H03K17/0822; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0142; H10D84/02; H10D84/03; H10D84/038; H10D84/101; H10D84/141; H10D84/80; H10D84/811; H10D84/82; H10D84/83; H10D84/83138; H10D84/837; H10D84/839; H10D89/00; H10D89/60; H10D89/601; H10D84/8311
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
148 words
A semiconductor integrated circuit device, comprising: a vertical type MOS FET formed in a semiconductor substrate in such a manner that the semiconductor substrate constitutes the drain region thereof, said vertical type MOS FET being connected to a load for switching on and off a current flowing through said load; a first lateral MOS FET formed in the drain region of said vertical type MOS FET, said first lateral type MOS FET being connected to said vertical type MOS FET to protect the latter from an excessive current which tends to flow when said load is short-circuited; and a second lateral type MOS FET formed in the drain region of said vertical type MOS FET, said second lateral type MOS FET being adapted to be used as an element in a detection-control circuit for controlling said first lateral type MOS FET by detecting the short-circuit of said load.
Claim 2
Dependent Claim
148 words
A semiconductor integrated circuit device, comprising: a vertical type MOS FET formed in a semiconductor substrate in such a manner that the semiconductor substrate constitutes the drain region thereof, said vertical type MOS FET being connected to a load for switching on and off a current flowing through said load; a first lateral MOS FET formed in the drain region of said vertical type MOS FET, said first lateral type MOS FET being connected to said vertical type MOS FET to protect the latter from an excessive current which tends to flow when said load is short-circuited; and a second lateral type MOS FET formed in the drain region of said vertical type MOS FET, said second lateral type MOS FET being adapted to be used as an element in a detection-control circuit for controlling said first lateral type MOS FET by detecting the short-circuit of said load.
Claim 3
Dependent Claim
162 words
A semiconductor integrated circuit device according to claim 1, wherein: said vertical type MOS FET has the drain thereof connected to said load, the source thereof grounded and the gate thereof connected to a switching control signal input terminal through a first resistor, said first lateral type MOS FET having the drain thereof connected to the gate of said vertical . type MOS FET and the source thereof grounded, said second lateral type MOS FET having the drain and the gate thereof connected together and to said input terminal and the source thereof connected to the gate of said first lateral type MOS FET; and said detection-control circuit comprises said second lateral type MOS FET, a first capacitor connected between the source of said second lateral type MOS FET and ground, and a diode having the cathode thereof connected to the drain of said vertical type MOS FET and the anode thereof connected to the source of said second lateral MOS FET.
Claim 4
Dependent Claim
85 words
A semiconductor integrated circuit device according to claim 2, wherein: said second lateral type MOS FET has the channel forming region thereof and the source thereof connected together; said first capacitor is constituted by an insulating thin layer provided on the source region of said second lateral type MOS FET, and a conductor layer provided on said insulating thin layer; and said diode is constituted by a pn junction between the channel forming region of said second lateral type MOS FET and said semiconductor substrate.
Claim 5
Dependent Claim
202 words
A semiconductor integrated circuit device according to claim 1, further comprising a third lateral type MOS FET formed in the drain of said vertical type MOS FET, wherein: said vertical type MOS FET has the drain thereof connected to said load, the source thereof grounded and the gate thereof connected to a switching control signal input terminal through a first resistor, said first lateral type MOS FET having the drain thereof connected to the gate of said vertical type MOS FET and the source grounded, said second lateral type MOS FET having the drain thereof connected to the gate of said first lateral type MOS FET and the source thereof grounded, said third lateral type MOS FET having the drain thereof connected to the gate of said second lateral type MOS FET, the gate thereof connected to said input terminal and the source thereof grounded; and said detection-control circuit comprises said second lateral type MOS FET, said third lateral type MOS FET, a second capacitor connected between the drain and the source of said third lateral type MOS FET, and a second resistor connected between the drain of vertical type MOS FET and the drain of said second lateral type MOS FET.
Claim 6
Dependent Claim
191 words
A semiconductor integrated circuit device according to claim 1, wherein: said vertical type MOS FET has the drain thereof connected to said load, the gate thereof connected to a switching control signal input terminal through a first resistor and the source thereof grounded, said first lateral type MOS FET having the drain thereof connected to the gate of said vertical type MOS FET and the source thereof grounded, said second lateral MOS FET having the source grounded; said detection-control circuit comprises a comparator for comparing the gate voltage of said vertical type MOS FETwith a reference voltage, an AND circuit to which are applied the output signal of said comparator and the drain voltage of said vertical type MOS FET, and a latch circuit for holding and imparting the output of said AND circuit to the gate of said first lateral type MOS FET; and said comparator, said AND circuit and said latch circuit are constituted by a plurality of source-grounded lateral type MOS FET's including said second lateral type MOS FET, said plurality of lateral type MOS FET's being formed in the drain region of said vertical type MOS FET.
Claim 7
Independent Claim
250 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) providing an n type semiconductor substrate; (b) forming an insulating thin layer on a main surface of said semiconductor substrate; (c) implanting p type impurity ions into a first region, which is exposed at said main surface, of said semiconductor substrate through said insulating thin layer; (d) forming a first and second conductor layer on said insulating thin layer; (e) implanting p type impurity ions into said first region and a second region, which is exposed at said main surface and spaced apart from said first region, of said semiconductor substrate through said insulating thin layer; (f) heating said semiconductor substrate to cause said p type impurity ions to be diffused, thereby forming a first and a second p type semiconductor region in said first and second regions in such a manner as to be exposed at said main surface, respectively; (g) implanting n type impurity ions into said first and second p type semiconductor region through said insulating thin layer; and (h) heating said semiconductor substrate to cause said n type impurity ions to be diffused, thereby forming a first and a second n type semiconductor region in said first p type semiconductor region in such a manner as to be exposed at said main surface and spaced apart from each other, while at the same time forming a third n type semiconductor region in such a manner as to exposed at said main surface.
Claim 8
Independent Claim
250 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) providing an n type semiconductor substrate; (b) forming an insulating thin layer on a main surface of said semiconductor substrate; (c) implanting p type impurity ions into a first region, which is exposed at said main surface, of said semiconductor substrate through said insulating thin layer; (d) forming a first and second conductor layer on said insulating thin layer; (e) implanting p type impurity ions into said first region and a second region, which is exposed at said main surface and spaced apart from said first region, of said semiconductor substrate through said insulating thin layer; (f) heating said semiconductor substrate to cause said p type impurity ions to be diffused, thereby forming a first and a second p type semiconductor region in said first and second regions in such a manner as to be exposed at said main surface, respectively; (g) implanting n type impurity ions into said first and second p type semiconductor region through said insulating thin layer; and (h) heating said semiconductor substrate to cause said n type impurity ions to be diffused, thereby forming a first and a second n type semiconductor region in said first p type semiconductor region in such a manner as to be exposed at said main surface and spaced apart from each other, while at the same time forming a third n type semiconductor region in such a manner as to exposed at said main surface.
Claim 9
Independent Claim
22 words
A method of manufacturing a semiconductor integrated circuit device according to calim 6, wherein said p type impurity ions comprise boron ions.
Claim 10
Independent Claim
22 words
A method of manufacturing a semiconductor integrated circuit device according to calim 6, wherein said p type impurity ions comprise boron ions.
Claim 11
Dependent Claim
22 words
A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said n type impurity ions comprise phosphorus ions.
Claim 12
Dependent Claim
25 words
A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said first and second conductor layers are formed of polycrystalline silicon.
References Cited (Backward Citations)
No citation records indexed.
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