EP0087785A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microprogram controlled data processing apparatus
Assignee: Hitachi Ltd
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Filing: 1983-02-25
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Granted: —
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Expires: 2003-02-25
Abstract
Abstract A microprogram controlled data processing apparatus for executing variable length instructions in which a operand specifier (OSP1, OSP2) for specifying an addressing mode of an operand is independent from an operation code (OP) for ascertaining an operation is disclosed. An instruction execution unit (800) receives a start address of a microprogram from a decoding unit (500), a destination operand ready status signal, a signal indicating whether a destination operand is in a general purpose register or in a memory unit (301, 303) and a destination operand address ready status signal from an operand memory access unit (700) to write into a destination operand address under control of a microprogram.
Inventors
- 👤 Hidekazu Matsumoto
- 👤 Tadaaki Bandoh
- 👤 Ryosei Hiraoka
- 👤 Takayuki Morioka
- 👤 Yoshihiro Miyazaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 04:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/3016; G06F9/38; G06F9/3824
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
242 words
A microprogram controlled data processing apparatus for executing variable length instructions in which an operand specifier (OSPl, OSP2) for specifying an addressing mode of an operand is independent from an operation code (OP) for ascertaining an operation, comprising: (a) memory means (301, BM1, BM2) for storing instructions and operands; (b) instruction fetch means (400) connected to said memory means for prefetching and holding an instruction; (c) decoding means (500) connected to said instruction fetch means for decoding an operation code (OP) and an operand specifier (OSP1, OSP2) contained in said instruction; (d) address calculation means (600) connected to said decoding means for calculating an effective address of the operand based on received address calculation information; (e) operand memory access means (700) connected to said memory means (BM2), said decoding means and said address calculation means for accessing said memory means in accordance with an operand ready control signal from said decoding means and the operand address from said address calculation means; and (f) instruction execution means (800) connected to said decoding means, and said operand memory access means for writing data to a destination operand address under control of a microprogram in accordance with a start address of the microprogram from said decoding means, and a source operand ready status signal, a signal indicating whether the destination operand is in general purpose registers or in said memory means and a destination operand address ready status signal from said operand memory access means.
Claim 2
Dependent Claim
242 words
A microprogram controlled data processing apparatus for executing variable length instructions in which an operand specifier (OSPl, OSP2) for specifying an addressing mode of an operand is independent from an operation code (OP) for ascertaining an operation, comprising: (a) memory means (301, BM1, BM2) for storing instructions and operands; (b) instruction fetch means (400) connected to said memory means for prefetching and holding an instruction; (c) decoding means (500) connected to said instruction fetch means for decoding an operation code (OP) and an operand specifier (OSP1, OSP2) contained in said instruction; (d) address calculation means (600) connected to said decoding means for calculating an effective address of the operand based on received address calculation information; (e) operand memory access means (700) connected to said memory means (BM2), said decoding means and said address calculation means for accessing said memory means in accordance with an operand ready control signal from said decoding means and the operand address from said address calculation means; and (f) instruction execution means (800) connected to said decoding means, and said operand memory access means for writing data to a destination operand address under control of a microprogram in accordance with a start address of the microprogram from said decoding means, and a source operand ready status signal, a signal indicating whether the destination operand is in general purpose registers or in said memory means and a destination operand address ready status signal from said operand memory access means.
Claim 3
Dependent Claim
98 words
A microprogram controlled data processing apparatus according to Claim 1 wherein said operand memory access means (700) includes a memory access controller (710), and said memory access controller receives the operand ready control signal from said decoding means (500) and a start of memory write signal from said instruction execution means (800), sends a start of memory read signal and a start of memory write signal to said memory means (301), and produces the source operand ready status signal and the signal indicating whether the destination operand is in the general purpose register or in said memory means.
Claim 4
Dependent Claim
105 words
A microprogram controlled data processing apparatus according to Claim 2 wherein said operand memory access means (700) includes a first flag register (725) for indicating a ready status of the memory address of the destination operand, a second flag (745) register for indicating whether the destination operand is in the general purpose register or in said memory means and a third flag (735) register for indicating the ready status of the source operand, and said first flag register is set by the operand address ready signal from said address calculation means and said second and third flag registers are set by said memory access controller.
Claim 5
Dependent Claim
79 words
A microprogram controlled data processing apparatus according to Claim 1 wherein said instruction execution means (800) includes a microprogram controller (810), and said microprogram controller instructs to start memory write access to said operand memory access means (700) when a microprogram under execution assumes a predetermined pattern in response to the reception of a destination operand address ready status signal and a signal indicating that the destination operand is in said memory means, from said operand memory access means.
Claim 6
Dependent Claim
78 words
A microprogram controlled data processing apparatus according to Claim 1 wherein said instruction execution means (800) includes a microprogram controller (810), and said microprogram controller instructs to start memory write access to said general purpose register when a microprogram under execution assumes a predetermined pattern in response to the reception of a destination operand address ready status signal and a signal indicating that the destination operand is in said general purpose register, from said operand memory access means.
References Cited (Backward Citations)
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