EP0087754A2
Expired / Lapsed
EP
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Semiconductor dynamic memory device
Assignee: Toshiba Corp
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Filing: 1983-02-23
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Granted: —
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Expires: 2003-02-23
Abstract
Abstract A semiconductor dynamic memory device includes a plurality of memories (12-1 to 12-4), row decoders (16-1 to 16-4) for selecting the row of the memories, column decoders (14-1 and 14-2) for selecting the column of memories, and sense amplifier circuits (18-1 to 18-4) connected to the memories, respectively. The dynamic memory device further has a driving circuit (24) for selectively activating some of the sense amplifier circuits (18-1 to 18-4) in accordance with the content of a predetermined bit of row address data supplied to the row decoders.
Inventors
- 👤 Syuso 313 Toshiba-Komukai-Jutaku Fujii
- 👤 Shozo Saito
- 👤 Kenji Natori
- 👤 Tohru Furuyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 14:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/408; G11C11/4087; G11C11/4096; G11C5/00; G11C5/02; G11C5/025
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
170 words
A semiconductor dynamic memory device comprising 2 n (n is an integer and is 2 or more) memory means (12-1 to 12-4, Ml to M8) each including a plurality of memory cells arranged in a matrix form, and a plurality of word lines and data lines connected to said memory cells; decoding means (14-1, 14-2, 16-1 to 16-4; RD-1 to RD-8, CD-1 to CD-4) for selecting rows and columns of said 2 n memory means in accordance with address data; and a plurality of sense amplifier circuits connected to said 2 n memory means (12-1 to 12-4, Ml to M8), respectively, for sensing and amplifying data on said data lines; characterized by further comprising driving means (24; 45) for selectively activating predetermined number of sense amplifier circuits in said plurality of sense amplifier circuits (18-1 to 18-4; SAl to SA8) in accordance with the content of at least one bit signal included in said address data and keeping the rest of said plurality of sense amplifier circuits in non-active state.
Claim 2
Dependent Claim
170 words
A semiconductor dynamic memory device comprising 2 n (n is an integer and is 2 or more) memory means (12-1 to 12-4, Ml to M8) each including a plurality of memory cells arranged in a matrix form, and a plurality of word lines and data lines connected to said memory cells; decoding means (14-1, 14-2, 16-1 to 16-4; RD-1 to RD-8, CD-1 to CD-4) for selecting rows and columns of said 2 n memory means in accordance with address data; and a plurality of sense amplifier circuits connected to said 2 n memory means (12-1 to 12-4, Ml to M8), respectively, for sensing and amplifying data on said data lines; characterized by further comprising driving means (24; 45) for selectively activating predetermined number of sense amplifier circuits in said plurality of sense amplifier circuits (18-1 to 18-4; SAl to SA8) in accordance with the content of at least one bit signal included in said address data and keeping the rest of said plurality of sense amplifier circuits in non-active state.
Claim 3
Dependent Claim
110 words
A semiconductor dynamic memory device according to claim l, characterized in that said decoding means includes 2 n row decoding circuits (16-1 to 16-4; RDl to RD8) respectively connected to said 2 n memory means (12-1 to 12-4; Ml to M8) and each connected to receive row address data, 2 (n-1) column decoding circuits (14-1 and 14-2; CDl to CD4) each connected to two of said 2 n memory means (12-1 to 12-4; Ml to M8), and logic means (30, 32, 34; 41 to 44) connected to permit column address data to be selectively transferred to said 2 ( n-1 ) column decoding circuits (14-1 to 14-2; CDl to CD4).
Claim 4
Dependent Claim
57 words
A semiconductor dynamic memory device according to claim 2, characterized in that said n is set at 2, and said logic means (30, 32 and 34) permits the column address data to be selectively transferred to said 2 (n-1) column decoding circuits (14-1 and 14-2) in accordance with a most significant bit in the row address data.
Claim 5
Dependent Claim
43 words
A semiconductor dynamic memory device according to claim 3, characterized in that said driving means (24) includes selection means for selecting two of said 2 n sense amplifier circuits (18-1 to 18-4) in accordance with a predetermined bit in the row address data.
Claim 6
Dependent Claim
43 words
A semiconductor dynamic memory device according to claim 2, characterized in that said driving means (24) includes selection means for selecting two of said 2 n sense amplifier circuits (18-1 to 18-4) in accordance with a predetermined bit in the row address data.
Claim 7
Dependent Claim
60 words
A semiconductor dynamic memory device according to claim 2, characterized in that said n is set at 3, and said logic means (41 to 44) permits the column address data to be selectively transferred to said 2 (n-1) column decoding circuits (CDl to CD4) in accordance with a most significant bit and a predetermined bit in the row address data.
Claim 8
Dependent Claim
47 words
A semiconductor dynamic memory device according to claim 6, characterized in that said driving means (45) includes selection means for selecting two of said 2 n sense amplifier circuits (SAl to SA8) in accordance with said predetermined bit and another predetermined bit in the row address data.
Claim 9
Dependent Claim
47 words
A semiconductor dynamic memory device according to claim 2, characterized in that said driving means (45) includes selection means for selecting two of said 2 n sense amplifier circuits (SAl to SA8) in accordance with said predetermined bit and another predetermined bit in the row address data.
References Cited (Backward Citations)
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