Means for preventing the breakdown of an insulation layer in semiconductor devices

Claim 2

A semiconductor device comprising a first conductor (11, R) disposed within an insulation layer of said semiconductor device characterized by further comprising a second conductor (25, 26, 27, 29) which is held at the same potential as said first conductor and arranged over said first conductor so as to mitigate the intensity of an electric field at the side edge portions of said first conductor.

Claim 3

A semiconductor device according to claim 1, characterized in that said first conductor is a gate electrode (11) or an MOS (Metal Oxide Semiconductor) transistor.

Claim 4

A semiconductor device according to claim 1, characterized in that said first conductor is a resistive layer (R, R 1 ) which electrically connects a first semiconductor element with a second semiconductor element.

Claim 5

A semiconductor device according to claim 1, characterized in that said second conductor is formed of aluminium or polycrystalline silicon.

Claim 6

A semiconductor device having a gate electrode (11) provided, through an insulation layer, on a portion of a semiconductor substrate located between a source region and a drain region, characterized in that said semiconductor device comprises a conductive layer means (25, 26 and 27) which is held at the same potential as said gate electrode (11) and which covers the regions above the side edge portions of said gate electrode located, at least, in the directions of said source region (lb) and said drain region (la), so as to mitigate the intensity of an electric field at said side edge portions.

Claim 7

A semiconductor device having a gate electrode (11) provided, through an insulation layer, on a portion of a semiconductor substrate located between a source region and a drain region, characterized in that said semiconductor device comprises a conductive layer means (25, 26 and 27) which is held at the same potential as said gate electrode (11) and which covers the regions above the side edge portions of said gate electrode located, at least, in the directions of said source region (lb) and said drain region (la), so as to mitigate the intensity of an electric field at said side edge portions.

Claim 8

The semiconductor device according to claim 5, characterized in that said conductive layer means is partially allowed to electrically contact said gate electrode and covers the regions above almost the whole upper surface of said gate electrode.

Claim 9

The semiconductor device according to claim 5, characterized in that said conductive means is formed of an aluminium layer.

Claim 10

The semiconductor device according to claim 5, characterized in that said conductive layer means is formed of a polycrystalline silicon layer.

Claim 11

The semiconductor device according to claim 5, characterized in that said conductive layer means includes a first conductive layer (26) and a second conductive layer (27), said first conductive layer being formed of a polycrystalline silicon layer part of which contacts said gate electrode and being allowed to cover the regions above the side edge portions of said gate electrode located, at least, in the directions of said source region and said drain region, so as to mitigate the intensity of an electric field at said side edge portions; said second conductive layer being formed of an aluminium layer part of which contacts said first conductive layer and being allowed to cover the regions above the side edge portions of said first conductive layer located, at least, in the directions of said source region and said drain region, so as to mitigate the intensity of an electric field at said side edge portions of said first conductive layer.

Claim 12

The semiconductor device according to claim 5, characterized in that said gate electrode is formed of polycrystalline silicon.

Claim 13

The semiconductor device according to claim 5, characterized in that said source region, drain region and gate electrode constitute an MOS transistor which receives from outside, an input signal for an MOS integrated circuit.

Claim 14

A semiconductor device including a resistive layer having a first end (8) for receiving an input signal from outside and a second end connected to a semiconductor element, said resistive layer being provided within an insulation layer on a semiconductor substrate, characterized in that said semiconductor device comprises a conductive layer (29) which is held at the same potential as said resistive layer (R, R 1 ) and which covers the region above the side edge portions of at least said first end (8) of said resistive layer, so as to mitigate the intensity of an electric field at said side edge portions.

Claim 15

A semiconductor device including a resistive layer having a first end (8) for receiving an input signal from outside and a second end connected to a semiconductor element, said resistive layer being provided within an insulation layer on a semiconductor substrate, characterized in that said semiconductor device comprises a conductive layer (29) which is held at the same potential as said resistive layer (R, R 1 ) and which covers the region above the side edge portions of at least said first end (8) of said resistive layer, so as to mitigate the intensity of an electric field at said side edge portions.

Claim 16

The semiconductor device according to claim 12, characterized in that said conductive layer is partially allowed to electrically contact said resistive layer (R) and covers the region above the whole upper surface of said resistive layer.

Claim 17

The semiconductor device according to claim 12, characterized in that said conductive layer covers, in a continuous manner, the region above said first end of said resistive layer and the region above the upper surface of a part of the resistive layer succeeding to said first end thereof.

Claim 18

The semiconductor device according to claim 12, characterized in that said conductive layer is connected to a bonding pad (5) for applying said input signal to said first end (8).

Claim 19

The semiconductor device according to claim 12, characterized in that said conductive layer (29) is formed of aluminium.

Claim 20

The semiconductor device according to claim 12, characterized in that said resistive layer (R, R 1 ) is formed of polycrystalline silicon.