EP0087008A2
Expired / Lapsed
EP
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Operation code decoding device with a plurality of programmable logic arrays
Assignee: International Business Machines Corp
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Filing: 1983-02-01
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Granted: —
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Expires: 2003-02-01
Abstract
Abstract The decoding device comprises a plurality of programmable logic arrays (20-24) operating in parallel, each to decode an operation code (OP code) of a given instruction class. A portion of the OP code is decoded by a decode multiplexer (40) to select one of the PLA's, and the decoded OP code from the selected PLA is gated through a N-way multiplexer (42) to provide the control code corresponding to the OP code.
Inventors
- 👤 Nandor G. Thoma
- 👤 Victor Stewart Moore
- 👤 Wayne Richard Kraft
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 06:14
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/267
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
114 words
An operation code decoding device including means (30) for providing operation code signals (31), a control code bus (44), and a programmable logic array means responsive to said operation code signals for generating control code signals therefrom, the decoding device being characterized in that said programmable logic array means comprises : a plurality of programmable logic arrays (20-24) each responsive to said operation code signals and concurrently operable for generating respective decoded output signals (25-29); and a decode multiplexer (40) further responsive to said operation code signals for selecting one of said plurality of programmable logic arrays and for gating the decoded output signals therefrom to said control code bus as control code signals.
Claim 2
Dependent Claim
114 words
An operation code decoding device including means (30) for providing operation code signals (31), a control code bus (44), and a programmable logic array means responsive to said operation code signals for generating control code signals therefrom, the decoding device being characterized in that said programmable logic array means comprises : a plurality of programmable logic arrays (20-24) each responsive to said operation code signals and concurrently operable for generating respective decoded output signals (25-29); and a decode multiplexer (40) further responsive to said operation code signals for selecting one of said plurality of programmable logic arrays and for gating the decoded output signals therefrom to said control code bus as control code signals.
Claim 3
Dependent Claim
55 words
The device according to claim 1 wherein each programmable logic array (20-24) is adapted to decode operation codes of a predetermined class, and said decode multiplexer (40) includes decode means for determining the class of a selected operation code and in response thereto for generating a select signal for selecting the corresponding programmable logic array.
Claim 4
Dependent Claim
16 words
The device according to claim 3 wherein said decode multiplexer (40) comprises a programmable logic array.
Claim 5
Independent Claim
38 words
The device according to'any one of the preceding Claims further comprising an N-way multiplexer (42) for receiving decoded output signals (25-29) from said programmable logic arrays (20-24), and providing control code signals on said control code bus (44).
Claim 6
Dependent Claim
34 words
The device according to Claim 4 in which said N-way multiplexer (42) is composed of field effect transistors the gates of which are controlled by gating signals (41) provided by said decode multiplexer (40).
References Cited (Backward Citations)
No citation records indexed.
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