Display device

Claim 2

A display device for displaying a desired symbol pattern and a graphic pattern by supplying predetermined signals to row and column lines connected to display elements of a row and a column among a plurality of display elements arranged in a matrix form, characterized in that said display device comprises: a display element array (1) which has m column display elements and n row display elements arranged at intersections between column lines (L21 - L 2n ) and row lines (L11 - L lm ) in a matrix form; a static shift register (15) which has m x n stages and is sequentially shifted in response to a clock signal which has m pulses and which is separated by a predetermined OFF period from another clock signal having m pulses; a switching circuit (10), connected to said shift register (15), for receiving a select signal and serial pixel data to supply the serial pixel data to a first stage of said shift register when the select signal is set at a first logic level and to feed back the serial pixel data in an end stage of said shift register to the first stage thereof when the select signal is set at a second logic level; first driving means (18) an output end of which is connected to said display element array (1) and an input end of which is connected to said shift register (15), said first driving means (18) being adapted to drive the row lines of said display element array (1) in accordance with outputs from the first to mth stages of said shift register (15); and second driving means (16, 17, 19) an output end of which is connected to said display element array (1), said second driving means (16, 17, 19) being reset to an initial status in response to a reset signal from an external signal source and being adapted to sequentially drive the column lines of said display element array (1) every time the m pulses of the clock signal are supplied thereto.

Claim 3

A device according to claim 1, characterized in that said second driving means (16, 17, 19) comprises: a binary counter (16) which is reset to an initial status in response to the reset signal in order to count the m pulses of the clock signal; and a decoder (17, 19) an input end of which is connected to said binary counter (16) and an output end of which is connected to said display element array (1), said decoder (17, 19) being adapted to sequentially produce scanning signals from output ends thereof which respectively correspond to the column lines of said display element array (1) every time said binary counter (16) counts the m pulses of the clock signal.

Claim 4

A display device for displaying a desired symbol pattern and a graphic pattern by supplying predetermined signals to row and column lines connected to display elements of a row and a column among a plurality of display elements arranged in a matrix form, characterized in that said display device comprises: a unit panel (4) having a plurality of unit display devices (3) arranged in a matrix form, each of said plurality of unit display devices (3) having a display element array (1) which has m column display elements and n row display elements arranged at intersections between column lines (L21 L2n) and row lines (L11 - L lm ) in a matrix form, a static shift register (15) which has m x n stages and is sequentially shifted in response to a clock signal which has m pulses and which is separated by a predetermined OFF period from another clock signal having m pulses, a switching circuit (10), connected to said shift register (15), for receiving a select signal and serial pixel data to supply the serial pixel data to a first stage of said shift register when the select signal is set at a first logic level and to feed back the serial pixel data in an end stage of said shift register to the first stage thereof when the select signal is set at a second logic level, first driving means (18) an output end of which is connected to said display element array (1) and an input end of which is connected to said shift register (15), said first driving means (18) being adapted to drive the row lines of said display element array (1) in accordance with outputs from the first to mth stages of said shift register (15), and second driving means (16, 17, 19) an output end of which is connected to said display element array (1), said second driving means (16, 17, 19) being reset to an initial status in response to a reset signal from an external signal source and being adapted to sequentially drive the column lines of said display element array (1) every time the m pulses of the clock signal are supplied thereto; a pixel data line (LD) and a reset signal line (LR) which are commonly connected to the plurality of unit display devices (3) of said unit panel (4); clock signal lines (LCl - LCM) each connected to unit display devices (3) of a corresponding column; select signal lines (LS1 - LSN) each connected to unit display devices (3) of a corresponding row; a unit driver (5), connected to said pixel data line (LD), said reset signal line (LR), said clock signal lines (LCl - LCM) and said select signal lines (LSl - LSN), for repeatedly supplying the m pulses of the clock signal respectively to said clock signal lines (LCl - LCM) and for sequentially switching the first and second levels of the select signal respectively supplied to said select signal lines (LSl - LSN) every time n clock signals each consisting of the m pulses are respectively supplied to the clock signal lines (LCl - LCM).

Claim 5

A display device for displaying a desired symbol pattern and a graphic pattern by supplying predetermined signals to row and column lines connected to display elements of a row and a column among a plurality of display elements arranged in a matrix form, characterized in that said display device comprises: a unit panel (4) having a plurality of unit display devices (3) arranged in a matrix form, each of said plurality of unit display devices (3) having a display element array (1) which has m column display elements and n row display elements arranged at intersections between column lines (L21 L2n) and row lines (L11 - L lm ) in a matrix form, a static shift register (15) which has m x n stages and is sequentially shifted in response to a clock signal which has m pulses and which is separated by a predetermined OFF period from another clock signal having m pulses, a switching circuit (10), connected to said shift register (15), for receiving a select signal and serial pixel data to supply the serial pixel data to a first stage of said shift register when the select signal is set at a first logic level and to feed back the serial pixel data in an end stage of said shift register to the first stage thereof when the select signal is set at a second logic level, first driving means (18) an output end of which is connected to said display element array (1) and an input end of which is connected to said shift register (15), said first driving means (18) being adapted to drive the row lines of said display element array (1) in accordance with outputs from the first to mth stages of said shift register (15), and second driving means (16, 17, 19) an output end of which is connected to said display element array (1), said second driving means (16, 17, 19) being reset to an initial status in response to a reset signal from an external signal source and being adapted to sequentially drive the column lines of said display element array (1) every time the m pulses of the clock signal are supplied thereto; a pixel data line (LD) and a reset signal line (LR) which are commonly connected to the plurality of unit display devices (3) of said unit panel (4); clock signal lines (LCl - LCM) each connected to unit display devices (3) of a corresponding column; select signal lines (LS1 - LSN) each connected to unit display devices (3) of a corresponding row; a unit driver (5), connected to said pixel data line (LD), said reset signal line (LR), said clock signal lines (LCl - LCM) and said select signal lines (LSl - LSN), for repeatedly supplying the m pulses of the clock signal respectively to said clock signal lines (LCl - LCM) and for sequentially switching the first and second levels of the select signal respectively supplied to said select signal lines (LSl - LSN) every time n clock signals each consisting of the m pulses are respectively supplied to the clock signal lines (LCl - LCM).

Claim 6

A display device for displaying a desired symbol pattern and a graphic pattern by supplying predetermined signals to row and column lines connected to display elements of a row and a column among a plurality of display elements arranged in a matrix form, characterized in that said display device comprises: a display element array (1) which has m column display elements and n row display elements arranged at intersections between column lines (L21 - L 2n ) and row lines (L 11 - Llm) in a matrix form; a static shift register (15) which has m x n stages and is sequentially shifted in response to a clock signal which has m pulses and which is separated by a predetermined OFF period from another clock signal having m pulses; a switching circuit (10), connected to said shift register (15), for receiving a select signal and serial pixel data to supply the serial pixel data to a first stage of said shift register when the select signal is set at a first logic level and to feed back the serial pixel data in an end stage of said shift register to the first stage thereof when the select signal is at a second logic level; first driving means (18) an output end of which is connected to said display element array (1) and an input end of which is connected to said shift register (15), said first driving means (18) being adapted to drive the row lines of said display element array (1) in accordance with outputs from the first to mth stages of said shift register (15); second driving means (17, 19, 21, 22) an output end of which is connected to said display element array (1), said second driving means (17, 19, 21, 22) being reset to an initial status in response to a reset signal from an external signal source and being adapted to sequentially drive the column lines of said display element array (1) every time the m pulses of the clock signal are supplied thereto; and luminance controlling means (30), connected to said second driving means (17, 19, 21, 22), for disabling said second driving means (17, 19, 21, 22) to drive the column lines during a period of a pulsed luminance control signal externally applied.

Claim 7

A display device for displaying a desired symbol pattern and a graphic pattern by supplying predetermined signals to row and column lines connected to display elements of a row and a column among a plurality of display elements arranged in a matrix form, characterized in that said display device comprises: a display element array (1) which has m column display elements and n row display elements arranged at intersections between column lines (L21 - L 2n ) and row lines (L 11 - Llm) in a matrix form; a static shift register (15) which has m x n stages and is sequentially shifted in response to a clock signal which has m pulses and which is separated by a predetermined OFF period from another clock signal having m pulses; a switching circuit (10), connected to said shift register (15), for receiving a select signal and serial pixel data to supply the serial pixel data to a first stage of said shift register when the select signal is set at a first logic level and to feed back the serial pixel data in an end stage of said shift register to the first stage thereof when the select signal is at a second logic level; first driving means (18) an output end of which is connected to said display element array (1) and an input end of which is connected to said shift register (15), said first driving means (18) being adapted to drive the row lines of said display element array (1) in accordance with outputs from the first to mth stages of said shift register (15); second driving means (17, 19, 21, 22) an output end of which is connected to said display element array (1), said second driving means (17, 19, 21, 22) being reset to an initial status in response to a reset signal from an external signal source and being adapted to sequentially drive the column lines of said display element array (1) every time the m pulses of the clock signal are supplied thereto; and luminance controlling means (30), connected to said second driving means (17, 19, 21, 22), for disabling said second driving means (17, 19, 21, 22) to drive the column lines during a period of a pulsed luminance control signal externally applied.

Claim 8

A display device according to claim 4, characterized in that said second driving means (17, 19, 21, 22) comprises a bit counter (21) which is reset to an initial status in response to the reset signal to produce a carry signal every time said bit counter (21) counts the m pulses of the clock pulse, an address counter (22), connected to said bit counter, for receiving the carry signal to sequentially produce address signals which specify the row lines to be driven of said display element array (1), and a decoder (17, 19), connected to said address counter (22), for sequentially producing scanning signals from output ends thereof corresponding to the address signals after said decoder (17, 19) receives the address signals; and said luminance controlling means (30) disables said decoder (17, 19) to produce the scanning signals when said luminance controlling means receives the luminance control signal.

Claim 9

A device according to claim 5, characterized in that said luminance controlling means (30) comprises: a first gate circuit (31) for passing the luminance control signal therethrough in response to an enable signal externally applied thereto; a second gate circuit (32) for passing the carry signal therethrough in response to the enable signal externally applied thereto; and a third gate circuit (33), connected to said first and second gate circuits (31, 32), for producing a luminance enable signal by mixing outputs from said first and second gate circuits (31, 32), whereby the scanning signals from said decoder (17, 19) are controlled by the luminance enable signal.

Claim 10

A display device for displaying a desired symbol pattern and a graphic pattern by suppling predetermined signals to row and column lines connected to display elements of a row and a column among a plurality of display elements arranged in a matrix form, characterized in that said display device comprises: a display element array (1) which has m column display elements and n row display elements arranged at intersections between column lines (L 21 - L 2n ) and ro w lines (L11 - L lm ) in a matrix form; a static shift register (15) which has m x n stages and is sequentially shifted in response to a clock signal which has m pulses and which is separated by a predetermined OFF period from another clock signal having m pulses; a switching circuit (10), connected to said shift register (15), for receiving a select signal and serial pixel data to supply the serial pixel data to a first stage of said shift register when the select signal is set at a first logic level and to feed back the serial pixel data in an end stage of said shift register to the first stage thereof when the select signal is set at a second logic level; first driving means (18) an output end of which is connected to said display element array (1) and an input end of which is connected to said shift register (15), said first driving means (18) being adapted to drive the row lines of said display element array (1) in accordance with outputs from the first to mth stages of said shift register (15); second driving means (17, 19, 21, 22) an output end of which is connected to said display element array (1), said second driving means (17, 19, 21, 22) being reset to an initial status in response to a reset signal from an external signal source and being adapted to sequentially drive the column lines-of said display element array (1) every time the m pulses of the clock signal are supplied thereto; and clearing means (23), connected to said second driving means (17, 19, 21, 22) and said static shift register (15), for multiplying the number of scanning operations of the rows by said second driving means (17, 19, 21, 22) by the number of pulsed luminance control signals externally applied, and for clearing contents of said shift register (15) when a multiplication value reaches a predetermined value.

Claim 11

A display device for displaying a desired symbol pattern and a graphic pattern by suppling predetermined signals to row and column lines connected to display elements of a row and a column among a plurality of display elements arranged in a matrix form, characterized in that said display device comprises: a display element array (1) which has m column display elements and n row display elements arranged at intersections between column lines (L 21 - L 2n ) and ro w lines (L11 - L lm ) in a matrix form; a static shift register (15) which has m x n stages and is sequentially shifted in response to a clock signal which has m pulses and which is separated by a predetermined OFF period from another clock signal having m pulses; a switching circuit (10), connected to said shift register (15), for receiving a select signal and serial pixel data to supply the serial pixel data to a first stage of said shift register when the select signal is set at a first logic level and to feed back the serial pixel data in an end stage of said shift register to the first stage thereof when the select signal is set at a second logic level; first driving means (18) an output end of which is connected to said display element array (1) and an input end of which is connected to said shift register (15), said first driving means (18) being adapted to drive the row lines of said display element array (1) in accordance with outputs from the first to mth stages of said shift register (15); second driving means (17, 19, 21, 22) an output end of which is connected to said display element array (1), said second driving means (17, 19, 21, 22) being reset to an initial status in response to a reset signal from an external signal source and being adapted to sequentially drive the column lines-of said display element array (1) every time the m pulses of the clock signal are supplied thereto; and clearing means (23), connected to said second driving means (17, 19, 21, 22) and said static shift register (15), for multiplying the number of scanning operations of the rows by said second driving means (17, 19, 21, 22) by the number of pulsed luminance control signals externally applied, and for clearing contents of said shift register (15) when a multiplication value reaches a predetermined value.

Claim 12

A display device according to claim 7, characterized in that said second driving means (17, 19, 21, 22) comprises a bit counter (21) which is reset to an initial status in response to the reset signal to produce a carry signal every time said bit counter (21) counts the m pulses of the clock pulse, an address counter (22), connected to said bit counter, for receiving the carry signal to sequentially produce address signals which specify the column lines to be driven of said display element array (1) and a page signal every time the addressing of all column lines is completed, and a decoder (17, 19), connected to said address counter (22), for sequentially producing scanning signals from output ends thereof corresponding to the address signals after said decoder (17, 19) receives the address signals; and said clearing means (23) comprises a gate circuit (27), connected to said address counter (22), for mixing a page signal from said address counter and the luminance control signal, and a preset counter (24, 25), connected to said gate circuit (27), for counting an output from said gate circuit (27) and for producing a clear signal to said shift register (15) when a count of said preset counter (24, 25) reaches a predetermined value.

Claim 13

A device according to claim 8, characterized in that said address counter (22) is reset to an initial status when said address counter (22) receives the reset signal and produces the page signals which correspond to the predetermined value.