EP0085916A2
Expired / Lapsed
EP
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Method of fabricating field effect transistors
Assignee: Hitachi Ltd
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Filing: 1983-01-28
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Granted: —
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Expires: 2003-01-28
Abstract
Abstract A field effect transistor fabricating method comprises the steps of forming an impurity region (23) for a channel in a surface portion of a semiconductor substrate (22); forming a first material layer (30) which has a width substantially equal to that of a gate electrode in a position on said semiconductor substrate where said gate electrode is to be formed, a second material layer (28) which has a larger width than said first material layer (30) above said first material layer, and source and drain regions (29) by ion implantation using said first and second material layers (30, 28) as a mask; forming source and drain electrodes (31) in contact with said source and drain regions (29); forming a third material layer (33) which has a selectivity with said first material layer (30) in its etching characteristics, on the semiconductor body thus far prepared; forming at least an aperture by removing said first material layer (30) in using said third material layer (33) as a mask; and forming said gate electrode (35) in said aperture.
Inventors
- 👤 Kiichi Ueyanagi
- 👤 Susumu Takahashi
- 👤 Yasunari Umemoto
- 👤 Michiharu Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/061; H10D30/0612; H10D30/0614; H10D30/60; H10D30/791; H10D30/797; H10D30/80; H10D30/87; H10P; H10P76/00; H10P76/40; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
171 words
A method of fabricating a field effect transistor, comprising: forming an impurity region (23) for a channel in a surface portion of a semiconductor substrate (22); forming a first material layer (30) which has a width substantially equal to that of a gate electrode, in a position on said semiconductor substrate where said gate electrode is to be formed, a second material layer (28) which has a larger width than said first material layer (30), above said first material layer, and source and drain regions (29) by ion implantation using said first and second material layers (30, 28) as a mask; forming source and drain electrodes (31) in contact with said source and drain regions (29); forming a third material layer (33) which has a selectivity with said first material layer (30) in its etching characteristics, on the semiconductor body thus far prepared; forming an aperture by removing said first material (30) in using said third material layer (33) as a mask; and forming said gate electrode (35) in said aperture.
Claim 2
Independent Claim
171 words
A method of fabricating a field effect transistor, comprising: forming an impurity region (23) for a channel in a surface portion of a semiconductor substrate (22); forming a first material layer (30) which has a width substantially equal to that of a gate electrode, in a position on said semiconductor substrate where said gate electrode is to be formed, a second material layer (28) which has a larger width than said first material layer (30), above said first material layer, and source and drain regions (29) by ion implantation using said first and second material layers (30, 28) as a mask; forming source and drain electrodes (31) in contact with said source and drain regions (29); forming a third material layer (33) which has a selectivity with said first material layer (30) in its etching characteristics, on the semiconductor body thus far prepared; forming an aperture by removing said first material (30) in using said third material layer (33) as a mask; and forming said gate electrode (35) in said aperture.
Claim 3
Dependent Claim
18 words
The method of claim 1, wherein said second material layer (28) is constructed of a plurality of sub-layers.
Claim 4
Dependent Claim
20 words
The method of claim 1 or 2, wherein said third material layer (33) is constructed of a plurality of sub-layers.
Claim 5
Dependent Claim
38 words
The method of claim 3, wherein said third material layer (33) is laminated of an inorganic material sub-layer, which has a selectivity with said first material layer (30) in its etching characteristics, and an organic high-molecular material sub-layer.
Claim 6
Dependent Claim
33 words
The method of claim 3, wherein said third material layer (33) is constructed of an organic high-molecular material layer which has a selectivity with said first material layer (30) in its etching characteristics.
Claim 7
Independent Claim
194 words
A method of fabricating a field effect transistor, comprising: forming an impurity region for a channel in a surface portion of a semiconductor substrate; forming a first material layer, which has a width substantially equal to that of a gate electrode, in a position on said semiconductor substrate where said gate electrode is to be formed, a second material layer, which has a larger width than said first material layer, above said first material layer, and source and drain regions by an ion implantation using said first and second material layers as a mask; forming an inorganic insulating layer on the semiconductor body thus far prepared; removing those regions of said inorganic insulating layer which are to be formed with source and drain electrodes; forming said source and drain electrodes in contact with said source and drain regions; forming a third material layer, which has a selectivity with said first material layer ' in its etching characteristics, on the semiconductor body thus far prepared by the foregoing steps; forming an aperture by removing said first material layer in using said third material layer as a mask; and forming said gate electrode in said aperture.
Claim 8
Independent Claim
194 words
A method of fabricating a field effect transistor, comprising: forming an impurity region for a channel in a surface portion of a semiconductor substrate; forming a first material layer, which has a width substantially equal to that of a gate electrode, in a position on said semiconductor substrate where said gate electrode is to be formed, a second material layer, which has a larger width than said first material layer, above said first material layer, and source and drain regions by an ion implantation using said first and second material layers as a mask; forming an inorganic insulating layer on the semiconductor body thus far prepared; removing those regions of said inorganic insulating layer which are to be formed with source and drain electrodes; forming said source and drain electrodes in contact with said source and drain regions; forming a third material layer, which has a selectivity with said first material layer ' in its etching characteristics, on the semiconductor body thus far prepared by the foregoing steps; forming an aperture by removing said first material layer in using said third material layer as a mask; and forming said gate electrode in said aperture.
References Cited (Backward Citations)
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