← Back to Patent Explorer
EP0085395A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

High density memory cell

Assignee: AT&T Inc
•
Filing: 1983-01-26
•
Granted: —
•
Expires: 2003-01-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Memory cell spacing can be reduced by using the diffused capacitance enhancement layer (22) of a so-called hi-C cell as the isolating element between adjacent charge storage regions. This allows elimination of the field oxide (21) normally used for this function. Elimination of the field oxide permits closer packing of the cells.

Inventors

  • 👤 Richard Joseph Mcpartland
  • 👤 Walter Rosenzweig
  • 👤 Arnold William Yanof

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 18:20
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10D; H10D84/00; H10B; H10B12/00; H10B12/30

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 114 words
A semiconductor device comprising an array of closely packed storage cells (e.g. 30, 31, 22) each cell including a storage element which comprises a conductor (e.g. 58) insulated from a semiconductor storage region (e.g. 55, 53), said array further including regions of field insulator (e.g. 52) separating adjacent storage cells, CHARACTERIZED IN THAT closely adjacent storage elements of different storage cells share a common conductor (e.g. 58), each storage element comprising a shallow region (e.g. 55, 56) of one conductivity type and an underlying heavily doped region (e.g. 53) of the opposite conductivity type, the portion of the array between the adjacent storage regions and underlying the common conductor being devoid of field insulator.
Claim 2
Dependent Claim 114 words
A semiconductor device comprising an array of closely packed storage cells (e.g. 30, 31, 22) each cell including a storage element which comprises a conductor (e.g. 58) insulated from a semiconductor storage region (e.g. 55, 53), said array further including regions of field insulator (e.g. 52) separating adjacent storage cells, CHARACTERIZED IN THAT closely adjacent storage elements of different storage cells share a common conductor (e.g. 58), each storage element comprising a shallow region (e.g. 55, 56) of one conductivity type and an underlying heavily doped region (e.g. 53) of the opposite conductivity type, the portion of the array between the adjacent storage regions and underlying the common conductor being devoid of field insulator.
Claim 3
Dependent Claim 13 words
The device of claim 1 FURTHER CHARACTERIZED IN THAT the conductor comprises polysilicon.
Claim 4
Dependent Claim 15 words
The device of claim 1 FURTHER CHARACTERIZED IN THAT the conductor comprises a metal silicide.
Claim 5
Dependent Claim 15 words
The device of claim 1 FURTHER CHARACTERIZED IN THAT the insulating material is silicon dioxide.
Claim 6
Dependent Claim 36 words
The device of claim 1 FURTHER CHARACTERIZED IN THAT the heavily doped region (e.g. 22) is a capacitance enhancement layer contained in a semiconductor body (e.g. 20) of the same conductivity type but of lighter doping.
Claim 7
Dependent Claim 26 words
The device of claim 5 FURTHER CHARACTERIZED IN THAT the distance corresponding to the region separating storage regions of adjacent cells is less than 3 microns.
Claim 8
Dependent Claim 23 words
The device of claim 6 FURTHER CHARACTERIZED IN THAT a single continuous capacitance enhancement layer is common to at least two storage elements.
Claim 9
Dependent Claim 23 words
The device of claim 1 FURTHER CHARACTERIZED IN THAT a separate capacitance enhancement layer (e.g. Fig. 8) is provided for each storage element.
Claim 10
Dependent Claim 71 words
The device of claim 1 FURTHER CHARACTERIZED IN THAT a source region (e.g. 30) of the same conductivity type as that of the shallow layer of the storage region, spaced from the shallow layer by a channel (e.g. 33) having the opposite conductivity type, and a gate (e.g. 31) overlying the channel so that, with appropriate voltage applied to the gate, charge is transferred from the source to the storage region.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag