Electronic postage meter arrangement controlled by a microprocessor system

Claim 2

A microprocessor system for an electronic postage meter characterised by: at least one microprocessor (10; 60, 61) connected to a plurality of address lines (22, 24; 64), a plurality of data lines (23, 25; 65), and control line means; and random access memory means (20, 21) connected to said address and data lines and to said control line means to enable storage of data in said memory means and reading of data from said memory means under control of said microprocessor, said random access memory means comprising first (20) and second (21) random access memories each connected to separate groups of said address lines and separate groups of said data lines, whereby data may be transferred to and from said first and second random access memories independently of any common interconnection.

Claim 3

A system according to claim 1 characterised by permanent memory means (11; 62, 63) for storing postage meter program routines for controlling the or each microprocessor, said routines addressing said first and second random access memories time sequentially for transfer of identical data thereto.

Claim 4

A system according to claim 1 characterised by permanent memory means having programs for controlling the or each microprocessor, said programs addressing said first and second random access memories with time overlap, to transfer the identical data to and from said first and second random access memories respectively, whereby identical data is transferred to and from said first and second random access 'memories at different times while both of said random access memories are addressed in a plurality of successive addressing cycles of the or each microprocessor.

Claim 5

A microprocessor system for an electronic postage meter and characterised by: a microprocessor (10; 80) with a plurality of address lines and a plurality of data lines, and control line means, and random access memory means (20, 21) connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor; a printer means (12; 82) connected to be controlled by said microprocessor; and feedback means (18; 83) for signalling the setting of the printer means to the microprocessor, wherein said random access memory comprises first (20) and second (21) random access memories; and means independently responsive to feedback from said feedback means to update the accounting data in each of said first and second random access memories.

Claim 6

A microprocessor system for an electronic postage meter and characterised by: a microprocessor (10; 80) with a plurality of address lines and a plurality of data lines, and control line means, and random access memory means (20, 21) connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor; a printer means (12; 82) connected to be controlled by said microprocessor; and feedback means (18; 83) for signalling the setting of the printer means to the microprocessor, wherein said random access memory comprises first (20) and second (21) random access memories; and means independently responsive to feedback from said feedback means to update the accounting data in each of said first and second random access memories.

Claim 7

' A microprocessor system for an electronic postage meter characterised by: a printing means (80, 81, 82); first and second microprocessors (60, 61); first and second accounting memories (20, 21) connected to be separately controlled by said first and second microprocessors, said first and second microprocessors having program routines for separately updating their respective accounting memories to account for the printing of postage by said printing means; and means for comparing the accounting results in said first and second accounting memories for disabling said postage meter in the absence of a valid comparison.

Claim 8

' A microprocessor system for an electronic postage meter characterised by: a printing means (80, 81, 82); first and second microprocessors (60, 61); first and second accounting memories (20, 21) connected to be separately controlled by said first and second microprocessors, said first and second microprocessors having program routines for separately updating their respective accounting memories to account for the printing of postage by said printing means; and means for comparing the accounting results in said first and second accounting memories for disabling said postage meter in the absence of a valid comparison.

Claim 9

A system according to claim 5 characterised in that said routines of said first and second microprocessors are arranged to store data in their respective accounting memories with different coding.

Claim 10

A system according to claim 5 or 6 characterised in that said printing means comprises a further microprocessor ( 8 0) having a postage printing program for controlling printing of said postage meter.

Claim 11

A microprocessor system for an electronic postage meter characterised by: a microprocessor (10); register means (20, 21) coupled to said microprocessor for storing postage accounting data; a plurality of sensors (50, 51, 52) for detecting operation conditions in said postage meter; said microprocessor being arranged to check said sensors periodically during operation; and means responsive to the absence of a unique pattern of said sensors for indicating an error condition.

Claim 12

A microprocessor system for an electronic postage meter characterised by: a microprocessor (10); register means (20, 21) coupled to said microprocessor for storing postage accounting data; a plurality of sensors (50, 51, 52) for detecting operation conditions in said postage meter; said microprocessor being arranged to check said sensors periodically during operation; and means responsive to the absence of a unique pattern of said sensors for indicating an error condition.

Claim 13

A microprocessor system characterised by an address bus (22, 24) having a plurality of address lines; a data bus (23, 25) having a plurality of data lines; a control bus having a plurality of control lines; a microprocessor (10) connected to each of the address lines of data lines of said address and data bus, and coupled to said control bus; and first and second random access memories (20, 21) each connected to different lines of said address bus and different lines of said data bus, whereby said random access memories may be separately addressed.

Claim 14

A microprocessor system characterised by an address bus (22, 24) having a plurality of address lines; a data bus (23, 25) having a plurality of data lines; a control bus having a plurality of control lines; a microprocessor (10) connected to each of the address lines of data lines of said address and data bus, and coupled to said control bus; and first and second random access memories (20, 21) each connected to different lines of said address bus and different lines of said data bus, whereby said random access memories may be separately addressed.

Claim 15

A system according to claim 9 characterised by a program memory (11) for controlling the operation of said microprocessor (10) and having a program for addressing said first and second random access memories (20, 21) to store the same data therein.

Claim 16

ll. A system according to claim 10 characterised in that said program addresses correspond to storage locations of said first and second memories (20, 21), corresponding data being stored therein or read therefrom at different times.

Claim 17

A system according to claim 11 characterised in that said program simultaneously stores different data in said first and second memories (20, 21) at noncorresponding address locations, whereby instantaneously occurring errors affect the data stored in said first and second memories in different manners.

Claim 20

An accounting system characterised by a microprocessor system according to any one of the preceding claims.

Claim 21

A postage meter characterised by an accounting system according to claim 15.