Oscillator with switched configuration

Claim 2

An oscillator comprising: A plurality of transistors, each said transistor comprising a gate, a source, and a drain, said respective sources of all of said transistors being electrically common, and said respective drains of all of said transistors being electrically common, and each of said respective gates being RF-coupled to and DC-isolated from the others of said respective gates; and means, connected to at least one of said gates, for selectably biasing at least one but less than all of said transistors to pinch-off.

Claim 3

The oscillator of Claim 1, wherein an inductive reactance is interposed between said respective gates, whereby voltages on said gates are out of phase when said selective pinch-off means has not pinched-off said gates.

Claim 4

The oscillator of Claim 2 comprising only two of said transistors, the respective voltages on said respecting gates being 180 degrees out of phase when both said transistors are not pinched-off.

Claim 5

The oscillator of Claim 1 wherein a respective large capacitance is interposed between respective ones of gates, whereby said gates are DC-isolated.

Claim 6

The oscillator of Claim 4, wherein each said respective gate is directly connected to said respective capacitor, and further comprising: an inductive reactance interposed between said gates and ground.

Claim 7

The oscillator of Claim 5, wherein at least one of said transistors comprises a gate length which is unequal to the gate length of others of said transistors.

Claim 8

The oscillator of Claim 5, wherein said oscillator comprises three of said transistors

Claim 9

The oscillator of Claim 7, wherein said three transistors comprise respective gate lengths in the approximate ratio of 1:2:6.

Claim 10

A superheterodyne receiver, comprising: RF input means for receiving an RF signal; first oscillator means for providing a local oscillator frequency near the frequency of said RF signal; first downconversion means, connected to said RF input and local oscillator means, for generating a first 1F signal; second oscillator means for providing a second oscillator frequency near the frequency of said first 1F signal; and second downconversion means connected to said second oscillator means and said first downconversion means, for generating lower frequency signals; wherein each said oscillator means comprises a plurality of transistors, each said transistor comprising a gate, a source, and a drain, said respective sources of all of said transistors being electrically common, and said respective drains of all of said transistors being electrically common, and each of said respective gates being RF-coupled to and DC-isolated from the others of said respective gates; and means, connected to at least one of said gates, for selectably biasing at least one but less than all of said transistors to pinch-off.

Claim 11

A superheterodyne receiver, comprising: RF input means for receiving an RF signal; first oscillator means for providing a local oscillator frequency near the frequency of said RF signal; first downconversion means, connected to said RF input and local oscillator means, for generating a first 1F signal; second oscillator means for providing a second oscillator frequency near the frequency of said first 1F signal; and second downconversion means connected to said second oscillator means and said first downconversion means, for generating lower frequency signals; wherein each said oscillator means comprises a plurality of transistors, each said transistor comprising a gate, a source, and a drain, said respective sources of all of said transistors being electrically common, and said respective drains of all of said transistors being electrically common, and each of said respective gates being RF-coupled to and DC-isolated from the others of said respective gates; and means, connected to at least one of said gates, for selectably biasing at least one but less than all of said transistors to pinch-off.

Claim 12

The superheterodyne receiver of Claim 9, further comprising: second oscillator means for providing a second oscillator frequency near the frequency of said first 1F signal; and second downconversion means connected to said second oscillator means and said first downconversion means, for generating lower frequency signals; wherein said second oscillator means comprises: A plurality of transistors, each said transistor comprising a gate, a source, and a drain, said respective sources of all of said transistors being electrically common, and said respective drains of all of said transistors being electrically common, and each of said respective gates being RF-coupled to and DC-isolated from the others of said respective gates; and means, connected to at least one of said gates, for selectably biasing at least one but less than all of said transistors to pinch-off.

Claim 13

ll. The oscillator of Claim 1, 2, 3, 4, 5, 6, 7, or 8, wherein each said transistor is a MESFET.

Claim 14

The oscillator of Claim 11, wherein each said transistor comprises a GaAs channel region.

Claim 15

The receiver of Claim 9 or 10, wherein each said transistor is a MESFET.

Claim 16

The receiver of Claim 13, wherein each said transistor comprises a GaAs channel region.