High-voltage CMOS process

Claim 2

A high-voltage CMOS process, comprising the steps of: providing a silicon surface; providing N-type device regions in said surface; providing P-type device regions in said surface; depositing a moat masking layer on respective moat areas of said N-type and P-type device regions; applying a channel stop implant overall, said channel stop implant comprising at least 5x1012 cm-2 of boron at an energy of at least 45 keV; selectively oxidizing said silicon surface where not masked by said moat masking layer; stripping said moat masking layer; and forming desired NMOS and PMOS'devices in said respective moat regions.

Claim 3

The process of Claim 1, wherein said N-type device regions are doped with phosphorus in a concentration of at least 5x1015 c m-3.

Claim 4

The process of Claim 1, wherein said silicon surface comprises an epitaxial layer of silicon on a silicon substrate, said epitaxial layer having the same conductivity type as said substrate and said substrate being more heavily doped than said epitaxial layer.

Claim 5

The process of Claim 3, wherein said N-type device regions and said P-type device regions are both implanted into said epitaxial layer, and wherein said epitaxial layer and said substrate are both P-type.

Claim 6

The process of Claim 4, wherein said N-type device regions are doped with phosphorus to a concentration of at least 5x1015 c m-3.

Claim 7

The process of Claim 5, wherein said P -type device regions are doped with boron to a concentration in the range of lxl0 15 per cm 3 to 5x10 15 per cm 3 .

Claim 8

The process of Claim 4, wherein the steps of: implanting selected portions of said P-type device regions with both phosphorus and arsenic, said implanted phosphorus and arsenic being implanted to approximately equal ranges; and annealling said implanted phosphorus and arsenic.

Claim 9

The process of Claim 3, wherein said step of providing N-type device regions comprises implanting an N-type impurity into said silicon surface to form a junction depth of at least 2h microns; and wherein said step of forming PMOS devices comprises implanting boron into selected areas of said N-type device regions and then annealling said boron, said boron implant forming a source/drain junction which is less than 30% as deep as the junction formed by the undersurface of said N-type device region.

Claim 10

The process of Claim 4, wherein said epitaxial layer has a depth at least three times the depth of said N-type device regions.

Claim 11

The process of Claim 9, further comprising the step of: forming guard rings around the periphery of selected one of said N-type device regions, said guard rings comprising a heavy concentration of an N-type impurity.

Claim 12

A process for forming desired CMOS circuits for operating at an operating voltage expressed as (10+x), where x is in the range between 0 and 10, comprising the steps of: providing a heavily doped P-type silicon substrate; providing a P-type epitaxial layer on said substrate, said epitaxial layer having a thickness in microns of approximately 13+0.6x; implanting N-type impurities to form N-tanks, said N-tanks having a surface dopant concentration of approximately 1016 per cm3, and said tanks having a depth in microns of approximately 3+0.2x; implanting P-wells into selected areas of said epitaxial layer, said P-wells having a dopant concentration of approximately 2x1015 per cm 3 ; depositing a moat masking layer on respective moat areas of said N-tanks and of said P-wells, where devices are to be formed; applying a channel stop implant overall, said channel stop implant comprising at least 5x10 12 per cm2 of boron at an energy of at least 50 keV; selectively oxidizing said epitaxial layer where not masked by said moat masking layer, said oxidizing step being performed to form a field oxide having a thickness expressed in microns of at least 0.8'+ 0.06x; stripping said moat masking layer; forming NMOS source/drain regions in said P-wells, and forming PMOS source/drain regions in said N -tanks, said source/drain regions having a maximum depth in microns are 0.5 + 0.05x, respective pairs of said source/drain regions defining channel regions therebetween, and said channel regions having a length expressed in microns which is not less than 3 + 0.4x; depositing gate dielectrics atop said respective channel regions, said gate dielectrics having a minimum thickness expressed in nanometers of 60+4x; and depositing gates atop said respective gate dielectrics.

Claim 13

A process for forming desired CMOS circuits for operating at an operating voltage expressed as (10+x), where x is in the range between 0 and 10, comprising the steps of: providing a heavily doped P-type silicon substrate; providing a P-type epitaxial layer on said substrate, said epitaxial layer having a thickness in microns of approximately 13+0.6x; implanting N-type impurities to form N-tanks, said N-tanks having a surface dopant concentration of approximately 1016 per cm3, and said tanks having a depth in microns of approximately 3+0.2x; implanting P-wells into selected areas of said epitaxial layer, said P-wells having a dopant concentration of approximately 2x1015 per cm 3 ; depositing a moat masking layer on respective moat areas of said N-tanks and of said P-wells, where devices are to be formed; applying a channel stop implant overall, said channel stop implant comprising at least 5x10 12 per cm2 of boron at an energy of at least 50 keV; selectively oxidizing said epitaxial layer where not masked by said moat masking layer, said oxidizing step being performed to form a field oxide having a thickness expressed in microns of at least 0.8'+ 0.06x; stripping said moat masking layer; forming NMOS source/drain regions in said P-wells, and forming PMOS source/drain regions in said N -tanks, said source/drain regions having a maximum depth in microns are 0.5 + 0.05x, respective pairs of said source/drain regions defining channel regions therebetween, and said channel regions having a length expressed in microns which is not less than 3 + 0.4x; depositing gate dielectrics atop said respective channel regions, said gate dielectrics having a minimum thickness expressed in nanometers of 60+4x; and depositing gates atop said respective gate dielectrics.