FET circuits

Claim 2

A FET circuit comprising: a pair of inverters (Q 51 +Q 53 , Q 52 +Q 54 ), each inverter comprising an input-stage FET (Q 51 , Q 52 ) connected in a manner that the gate electrode is connected to receive output signal (at 54, 53) of the FET (Q 52 , Q 51 ) of the other inverter, the sources of said input-stage FETs (Q 51 , Q 52 ) being connected to a common-connection point (C), and current source means (R 55 ) connected between said common-connection point (C) and a power supply terminal (52).

Claim 3

A FET circuit in accordance with claim 1, wherein said power source terminal (52) is grounding terminal.

Claim 4

A FET circuit in accordance with claim 1, wherein said current supply means is a resister.

Claim 5

A FET circuit in accordance with claim 1, wherein said current source means is a source-drain circuit of another FET.

Claim 6

A FET circuit in accordance with claim 1, wherein the gate of said another FET is connected to its source.

Claim 7

A FET circuit in accordance with claim 5, wherein said current source means is a dual gate FET with its two gates connected to its source.

Claim 8

A FET circuit in accordance with claim 1, wherein said FETs are Schottky junction gate FETs.

Claim 9

A FET circuit comprising: a pair of inverters (Q 51 +Q 53 , Q 52 +Q 54 ), each inverter comprising an input-stage FET (Q 51 , Q 52 ) connected in a manner that the gate electrode is connected to receive output signal of the FET (Q 52 , Q 51 ) of the other inverter through a circuit having a FET (Q 54 , Q53) and the sources of said input-stage FETs - (Q51 Q 52 ) being connected to a common-connection point (C), and a resister (R 55 ) is connected between said common-connect point (C) and a power supply terminal (52), the input electrodes of said input-stage FETs (Q 51 , Q 52 ) being connected through respective resisters ( R 53 , R54) to another power supply terminal (55).

Claim 10

A FET circuit comprising: a pair of inverters (Q 51 +Q 53 , Q 52 +Q 54 ), each inverter comprising an input-stage FET (Q 51 , Q 52 ) connected in a manner that the gate electrode is connected to receive output signal of the FET (Q 52 , Q 51 ) of the other inverter through a circuit having a FET (Q 54 , Q53) and the sources of said input-stage FETs - (Q51 Q 52 ) being connected to a common-connection point (C), and a resister (R 55 ) is connected between said common-connect point (C) and a power supply terminal (52), the input electrodes of said input-stage FETs (Q 51 , Q 52 ) being connected through respective resisters ( R 53 , R54) to another power supply terminal (55).

Claim 11

A FET circuit in accordance with claim 8, wherein both the said power source terminals (52, 55) are common.

Claim 12

A FET circuit comprising: a pair of inverters (Q 51 +Q 53 , Q 52 +Q 54 ), each inverter comprising an input-stage FET (Q 51 , Q 52 ) connected in a manner that the gate electrode is connected to receive output signal (at 54, 53) of the FET (Q 52 , Q 51 ) of the other inverter through a circuit having a normally-on FET (Q 54 , Q 53 ) and at least one diode (D 52 , D51), the sources of said input-stage FETs (Q 51' Q 52 ) being connected to a common-connection point (C), and a resister (R 55 ) connected between said common-connection point (C) and a power source terminal (52), the input electrodes of said input-stage FETs (Q 51 , Q 52 ) being connected through respective resistors (R53, R54) to said power supply, terminal (52), a pair of FETs (Q 15 , Q 16 ) are connected by their sources to the input electrodes (gates 54, 53) of the inverter (Q 52 , Q 51 ), respectively, by their gates commonly to a terminal (15) of a given voltage and by their drains to respective write-in terminals (16, 17).

Claim 13

A FET circuit comprising: a pair of inverters (Q 51 +Q 53 , Q 52 +Q 54 ), each inverter comprising an input-stage FET (Q 51 , Q 52 ) connected in a manner that the gate electrode is connected to receive output signal (at 54, 53) of the FET (Q 52 , Q 51 ) of the other inverter through a circuit having a normally-on FET (Q 54 , Q 53 ) and at least one diode (D 52 , D51), the sources of said input-stage FETs (Q 51' Q 52 ) being connected to a common-connection point (C), and a resister (R 55 ) connected between said common-connection point (C) and a power source terminal (52), the input electrodes of said input-stage FETs (Q 51 , Q 52 ) being connected through respective resistors (R53, R54) to said power supply, terminal (52), a pair of FETs (Q 15 , Q 16 ) are connected by their sources to the input electrodes (gates 54, 53) of the inverter (Q 52 , Q 51 ), respectively, by their gates commonly to a terminal (15) of a given voltage and by their drains to respective write-in terminals (16, 17).

Claim 14

A FET composite circuit comprising: a first reset-set flip-flop (91) as a first stage and, a second reset-set flip-flop (92) as a second stage, said first reset-set flip-flop (91) and said second flip-flop (92) being connected in a manner that output terminals Q and Q of the former (91) are connected to the input terminals S and R of the latter (92), respectively, a clock input terminal C of the former (91) and a reference input terminal REF of the latter (92) are connected in common to a clock input terminal (93) of said composite circuit, a reference input terminal REF of the former (91) and a clock input terminal C of the latter (92) are connected in common to a first reference input terminal (94) of said composite circuit, a reset input terminal R of the former (91) is connected to a second reference input terminal (96), a set input terminal S of the former (91) is connected to a delay input terminal '(95) of the composite circuit, output terminals Q and Q of the latter (92) are connected to the output terminals (97 and 98) of the composite circuit, respectively, and each of said first reset-set flip-flop (91) and said second reset-set flip-flop (92) comprising a pair of inverters (Q 51 +Q 53 , Q 52 +Q 54 ), each inverter comprising an input-stage FET (Q 51' Q 52 ) connected in a manner that the gate electrode is connected to receive output signal ( at 54 , 53 ) of the FET (Q 52 , Q51 ) of the other inverter through a circuit having a FET, the sources of said input-stage FETs (Q 51 , Q 52 ) being connected to a common-connection point (C), and current source means (R 55 ) connected between said common-connection point (C) and a power source terminal (52).

Claim 15

A FET composite circuit comprising: a first reset-set flip-flop (91) as a first stage and, a second reset-set flip-flop (92) as a second stage, said first reset-set flip-flop (91) and said second flip-flop (92) being connected in a manner that output terminals Q and Q of the former (91) are connected to the input terminals S and R of the latter (92), respectively, a clock input terminal C of the former (91) and a reference input terminal REF of the latter (92) are connected in common to a clock input terminal (93) of said composite circuit, a reference input terminal REF of the former (91) and a clock input terminal C of the latter (92) are connected in common to a first reference input terminal (94) of said composite circuit, a reset input terminal R of the former (91) is connected to a second reference input terminal (96), a set input terminal S of the former (91) is connected to a delay input terminal '(95) of the composite circuit, output terminals Q and Q of the latter (92) are connected to the output terminals (97 and 98) of the composite circuit, respectively, and each of said first reset-set flip-flop (91) and said second reset-set flip-flop (92) comprising a pair of inverters (Q 51 +Q 53 , Q 52 +Q 54 ), each inverter comprising an input-stage FET (Q 51' Q 52 ) connected in a manner that the gate electrode is connected to receive output signal ( at 54 , 53 ) of the FET (Q 52 , Q51 ) of the other inverter through a circuit having a FET, the sources of said input-stage FETs (Q 51 , Q 52 ) being connected to a common-connection point (C), and current source means (R 55 ) connected between said common-connection point (C) and a power source terminal (52).