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EP0083815A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Lateral junction field effect transistor device

Assignee: Koninklijke Philips NV
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Filing: 1982-12-17
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Granted: —
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Expires: 2002-12-17
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Abstract

Abstract A lateral junction field effect transistor device comprises a substrate (11) of a first conductivity type and a semiconductor layer (12) of the second conductivity type. Furthermore the device includes both a surface semiconductor layer (16/20) of the first conductivity type located between the gate and drain contact regions (17/19, 15/21) of the device and a buried semiconductor layer (13) of the second conductivity type which extends beneath at least the drain contact region (15/21) and the surface semi-conductor layer (16/20) of the device. The buried layer (13) may be in the form of a continuous layer extending beneath the gate, source, and drain contact regions of the device as well as the surface semiconductor layer, or it may be provided in annular form with an aperture beneath the source and gate regions (18, 17/19). The annular central buried layer configuration (13A) may further include an additional buried layer portion (13B) extending beneath the source region (18) of the device. Devices having buried and surface layers in accordance with the invention feature improved high-voltage breakdown characteristics, enhanced conductivity in the "on" state, and the ability to operate in the source-follower mode.

Inventors

  • 👤 Barry Mana Singer

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-26 22:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106; H10D62/17; H10D62/213; H10D62/221; H10W; H10W15/00; H10W15/01

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 262 words
A semiconductor device with a junction field effect transistor of the lateral JFET type, comprising a semiconductor substrate (11) of a first conductivity type and having a relatively light doping level, a first semiconductor layer (12) of a second conductivity type opposite to that of the first on said substrate and having a relatively light doping .level, source, gate, and drain contact regions (18, 17/19, 15/21) located at the surface of said first semiconductor layer, the gate region (17/19) being of the first conductivity type, more heavily doped than said substrate, and located between the source and the drain contact regions (18, 15/21) which latter regions are of the second conductivity type and more heavily doped than said first layer, means for electrically isolating the lateral JFET device from adjacent portions of said first semiconductor layer (12) and a buried semiconductor layer (13) of said second conductivity type located between said first layer (12) and said substrate (11) and forming a p-n isolation junction (14) with said substrate, characterized in that said buried semiconductor layer (13) of the second conductivity type has a doping level greater than that of said first semiconductor layer (12), said buried layer (13) extending beneath at least said drain contact region (15/21) and a surface semiconductor layer (16/20) of said first conductivity type, said surface layer being located at the surface of said first layer (12) and between said gate and said drain contact regions (17/19, 15/21), said surface layer (16/20) having a doping level on the same order of magnitude as that of said substrate (11).
Claim 2
Dependent Claim 262 words
A semiconductor device with a junction field effect transistor of the lateral JFET type, comprising a semiconductor substrate (11) of a first conductivity type and having a relatively light doping level, a first semiconductor layer (12) of a second conductivity type opposite to that of the first on said substrate and having a relatively light doping .level, source, gate, and drain contact regions (18, 17/19, 15/21) located at the surface of said first semiconductor layer, the gate region (17/19) being of the first conductivity type, more heavily doped than said substrate, and located between the source and the drain contact regions (18, 15/21) which latter regions are of the second conductivity type and more heavily doped than said first layer, means for electrically isolating the lateral JFET device from adjacent portions of said first semiconductor layer (12) and a buried semiconductor layer (13) of said second conductivity type located between said first layer (12) and said substrate (11) and forming a p-n isolation junction (14) with said substrate, characterized in that said buried semiconductor layer (13) of the second conductivity type has a doping level greater than that of said first semiconductor layer (12), said buried layer (13) extending beneath at least said drain contact region (15/21) and a surface semiconductor layer (16/20) of said first conductivity type, said surface layer being located at the surface of said first layer (12) and between said gate and said drain contact regions (17/19, 15/21), said surface layer (16/20) having a doping level on the same order of magnitude as that of said substrate (11).
Claim 3
Dependent Claim 23 words
A semiconductor device as claimed in Claim 1, wherein said buried layer (13) also extends beneath said gate and source regions (17/19, 18).
Claim 4
Dependent Claim 62 words
A semiconductor device as claimed in Claim 1, wherein said buried layer (13) comprises first and second buried layer portions, said first buried layer portion (13A) extending beneath said drain contact region (15/21) and said surface layer (16/20), and said second buried layer portion (13B) extending beneath said source region (18) and being spaced apart from said first buried layer portion (13A).

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