EP0083785A2
Expired / Lapsed
EP
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Method of forming self-aligned field effect transistors in integrated circuit structures
Assignee: International Business Machines Corp
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Filing: 1982-12-27
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Granted: —
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Expires: 2002-12-27
Abstract
Abstract A process for forming self-aligned field effect transistor devices is described. A heavily doped conductive layer (20) and an insulator layer (21) are formed over a substrate (10). The multilayer structure is etched to result in a patterned conductive layer (20) having substantially vertical sidewalls. The pattern of the conductive layer is chosen to be located above the planned source/drain regions with openings at the locations of the field effect transistor channels, and extends over the isolation pattern. A very thin insulating layer (24) is formed on these vertical sidewalls. It is utilized to controll- ably reduce the channel length of the field effect transistor and is preferably doped with conductivity imparting impurities. The gate dielectric (34) is formed on the channel surface. The source/drain regions (30) and a preferably lightly doped delimiting region (32) are simultaneously formed by thermal drive-in from the conductive layer (20) and sidewall insulating layer (24), respectively. The desired gate electrode (36) is then formed upon the gate dielectric.
Inventors
- 👤 Jacob Riseman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0273; H10D30/60; H10D30/0223; H10D30/0227; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/1414; H10P32/17; H10P32/171; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
168 words
A method of forming self-aligned field effect transistors in integrated circuit structures, characterized by the following steps: forming a heavily doped conductive layer (20) upon a monocrystalline silicon substrate (10); forming an insulator layer (21) upon the surface of said conductive layer; forming openings with substantially vertical sidewalls through said conductive layer to said silicon substrate in at least the locations of the planned gates of said field effect transistors; forming a sidewall insulator layer (24) upon the said vertical sidewalls of said conductive layer; heating the structure to form in said substrate the heavily doped portions of the sources/drains (30) of said field effect transistors by out-diffusion from said conductive layer; oxidizing the exposed said substrate to form the gate insulator (34) of said field effect transistors; forming the gate electrode (36) for each of said field effect transistors over said gate insulator; and forming electrical contacts through said insulator layer to the regions of said conductive layer (20) which are in electrical contact with said sources/drains.
Claim 2
Independent Claim
168 words
A method of forming self-aligned field effect transistors in integrated circuit structures, characterized by the following steps: forming a heavily doped conductive layer (20) upon a monocrystalline silicon substrate (10); forming an insulator layer (21) upon the surface of said conductive layer; forming openings with substantially vertical sidewalls through said conductive layer to said silicon substrate in at least the locations of the planned gates of said field effect transistors; forming a sidewall insulator layer (24) upon the said vertical sidewalls of said conductive layer; heating the structure to form in said substrate the heavily doped portions of the sources/drains (30) of said field effect transistors by out-diffusion from said conductive layer; oxidizing the exposed said substrate to form the gate insulator (34) of said field effect transistors; forming the gate electrode (36) for each of said field effect transistors over said gate insulator; and forming electrical contacts through said insulator layer to the regions of said conductive layer (20) which are in electrical contact with said sources/drains.
Claim 3
Dependent Claim
70 words
A method in accordance with claim 1, characterized in that said sidewall insulator layer (24) on said vertical sidewalls of the heavily doped conductive layer (20) is formed to consist of doped insulator material, and that when the structure is heated, lightly doped portions (32) of the sources/drains are formed by out- diffusion from said sidewall insulator layer (24) simultaneously with said formation of the heavily doped portions (30) .
Claim 4
Dependent Claim
65 words
A method in accordance with claim 1, characterized in that said sidewall insulator layer (24) is composed of chemical vapor deposited silicon dioxide which had been doped with N- conductivity imparting impurities, and said N- impurities outdiffuse from said sidewall insulator layer into said monocrystalline substrate (10) during said heating to form lightly doped portions (32) of the sources/ drains of said field effect transistors.
Claim 5
Dependent Claim
20 words
A method in accordance with claim 1 or 2, characterized in that said conductive layer (20) consists of polycrystalline silicon.
Claim 6
Dependent Claim
24 words
A method in accordance with claim 1, characterized in that said conductive layer (20) is a combination layer of polycrystalline silicon and metal silicide.
Claim 7
Dependent Claim
19 words
A method in accordance with claim 1, characterized in that said conductive layer (20) consists of a metal silicide.
Claim 8
Dependent Claim
38 words
A method in accordance with claim 1 or 2, characterized in that said sidewall insulator layer (24)-is between 150 to 1000 nanometers thick and effectively reduces the gate electrode and channel length to less than about 1000 nanometers.
Claim 9
Dependent Claim
60 words
A method in accordance with claim 1 or 2, characterized in that said conductive layer (24) consists of polycrystalline silicon which is doped to contain N+ type conductivity imparting impurity by an ion implantation process after its deposition using between about 1 x 1 0 15 to 1 x 10 16 ions/cm 2 at between about 30 to 100 keV.
Claim 10
Dependent Claim
16 words
A method in accordance with claim 8, characterized in that said conductivity imparting impurity is arsenic.
Claim 11
Dependent Claim
20 words
A method in accordance with claim 1, characterized in that said gate electrode (36) is composed of doped polycrystalline silicon.
Claim 12
Dependent Claim
44 words
A method in accordance with claim 1 or 2, characterized in that said field effect transistors are N channel, that said conductive layer (20) consists of polycrystalline silicon with N+ type doping, and the doping of said sidewall insulator layer (24) is N- type.
Claim 13
Dependent Claim
62 words
12i A method in accordance with claim 1 or 2, characterized in that said sidewall insulator layer (24) is formed by depositing a uniform thickness conformal layer of insulator material over said conductive layer (20) and the exposed substrate (10) and preferentially removing said insulating layer from the horizontal surfaces and leaving said sidewall insulator layer (24) upon said substantially vertical sidewalls.
References Cited (Backward Citations)
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