EP0083412A2
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EP
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Method and apparatus for encoding data
Assignee: International Business Machines Corp
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Filing: 1982-11-23
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Granted: —
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Expires: 2002-11-23
Abstract
Abstract An algorithm and the hardware embodiment for producing a run lenght limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of one zero and a maximum of seven zeros between adjacent 1's. The code is generated by a sequential scheme that maps two bits of unconstrained data into three bits of constrained data. The encoder is a finite state machine whose internal state description requires three bits. The encoder requires a looka- head of one future input vector (two bits) and a look back at the last channel bit generated during the immediately preceding encoding operation. The error propagation due to a random error is, at most, four bits in bursts of five. The hardware implementation is extremely simple and can operate at very high data speeds.
Inventors
- 👤 Peter Anthony C/O Ibm Corp. Franaszek
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 14:59
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; G06; G06T; G06T9/00; G06T9/005
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
113 words
A method for encoding a series of unconstrained binary input symbols into a run length limited (1,7) code having a 2/3 rate which comprises consecutively entering one new input symbol (X) comprising two bits into a logical tree coding network and simultaneously entering three state bits (Y) which were produced by the encoder during the immediately preceding encoding operation into the same encoding network and producing three channel output bits (Z) obeying said (1,7) encoding rules and three next state bits (Y') for use in the next succeeding coding operation, wherein the encoding of a given input symbol X is performed as a function of the next preceding input symbol X -1 .
Claim 2
Independent Claim
113 words
A method for encoding a series of unconstrained binary input symbols into a run length limited (1,7) code having a 2/3 rate which comprises consecutively entering one new input symbol (X) comprising two bits into a logical tree coding network and simultaneously entering three state bits (Y) which were produced by the encoder during the immediately preceding encoding operation into the same encoding network and producing three channel output bits (Z) obeying said (1,7) encoding rules and three next state bits (Y') for use in the next succeeding coding operation, wherein the encoding of a given input symbol X is performed as a function of the next preceding input symbol X -1 .
Claim 3
Dependent Claim
45 words
A method according to Claim 1, including mapping two of the state vector (Y) bits into said three channel bits (Z) as a function of the two current input bits (X) and one bit (z3), the least significant bit of the preceding channel symbol (Z).
Claim 4
Dependent Claim
81 words
A method according to Claim 2, in which the mapping of the state vector (Y) and the input vector (X) into the output vector (Z) and the next state vector (Y') is performed according to the mapping table of Figure 5, wherein the decimal values in the table are representative of the binary values manipulated by the method and wherein in the multibit binary vectors X, Y, Y' and Z, bits x2, y3, y3', and zl are the most significant bits.
Claim 5
Dependent Claim
49 words
A method according to Claim 3, including inserting a predetermined data input configuration into the input code stream to cause the state bits (Y) to assume a predetermined pattern whereby a predetermined channel symbol (Z) configuration is produced which is adapted for control use and for initializing the system.
Claim 6
Dependent Claim
166 words
An encoder for producing a run length limited (RLL) code for use in a structurally constrained environment, said code having a minimum of one and a maximum of seven 0's between adjacent l's and a coding rate 2/3, said encoder comprising means for receiving as an input vector (X) for a given encoding operation, two new message bits and a three bit state vector (Y) derived from the immediately preceding encoding operation, logic circuit means for producing a three bit constrained channel vector (Z), obeying said RLL coding rules and a three bit next-state vector (Y') which becomes the state vector (Y) for use in the next encoding operation, said logic circuit means producing the channel vector Z as a direct function of the two current input bits and the immediately preceding two input bits to said logic circuit means and forming the next-state vector as a catenation of the two current input bits and the least significant bit (z3) of the current channel vector (Z).
Claim 7
Dependent Claim
166 words
An encoder for producing a run length limited (RLL) code for use in a structurally constrained environment, said code having a minimum of one and a maximum of seven 0's between adjacent l's and a coding rate 2/3, said encoder comprising means for receiving as an input vector (X) for a given encoding operation, two new message bits and a three bit state vector (Y) derived from the immediately preceding encoding operation, logic circuit means for producing a three bit constrained channel vector (Z), obeying said RLL coding rules and a three bit next-state vector (Y') which becomes the state vector (Y) for use in the next encoding operation, said logic circuit means producing the channel vector Z as a direct function of the two current input bits and the immediately preceding two input bits to said logic circuit means and forming the next-state vector as a catenation of the two current input bits and the least significant bit (z3) of the current channel vector (Z).
Claim 8
Dependent Claim
29 words
An encoder according to Claim 5, in which the logic circuit means comprises a maximum of three functional logic levels and comprises conventional inverters, AND, OR, and NAND circuits.
Claim 9
Dependent Claim
90 words
An encoder according to Claim 5, in which the logic circuit means performs a mapping function to map the input vector X and the state vector Y into the output channel vector Z and the next-state vector Y' according to the mapping function table of Figure 5, wherein the decimal values in the table represent the binary data gated into and produced by the logic circuit means and wherein, in the multibit binary vectors X, Y, Y' and Z, bits x2, y3, y3', and zl are the most significant bits.
Claim 10
Dependent Claim
160 words
An encoding/decoding system for producing a run length limited (RLL) code for use in a structurally constrained environment, the code having a minimum of one and a maximum of seven 0's between adjacent l's and a coding rate 2/3, said system including an encoder according to claim 5, 6 or 7, and including a decoder for receiving a three bit input vector (K) for a given decoding operation and a six bit state vector J derived from the immediately preceding decoding operation, which comprises logic circuit means for producing a two bit unconstrained output vector (M) and a six bit next-state vector J' which- becomes the state vector J for use in the next decoding operation, said logic circuit means producing the output vector (M) as a function of the state vector (J) and the input vector (K) and producing the next-state vector J' as a catenation of the input vector (K) and a portion of the state vector (J).
Claim 11
Dependent Claim
96 words
A system according to claim 8, in which the decoder logic circuit means performs a mapping function to map the input vector K and state vector J into the output vector M and the next-state vector J', according to the two mapping function tables of Figures 9 and 10, the decimal values in the tables being representative of the data content in binary form, gated into and generated by the encoder logic circuit means, and wherein in the multibit vectors K, J, J' and M, bits k3, j6, y6' and m2 are the most significant bits.
References Cited (Backward Citations)
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