A semiconductor device which prevents soft errors

Claim 2

A semiconductor device, comprising: a semiconductor substrate (20) having a first type of conductivity; an impurity diffused layer having a second type of conductivity opposite to said first type of conductivity and being formed at the surface of said semiconductor substrate; an insulation layer (26) formed within said impurity diffused layer to divide said impurity diffused layer into a first impurity diffused layer (24 1 ) and a second impurity diffused layer (24 2 ) forming upper and lower layers electrically isolated from one another; and fixed voltage supply means (V cc ), electrically connected to said second impurity diffused layer, for supplying a fixed voltage to said second impurity diffused layer.

Claim 3

A semiconductor device according to claim 1 which includes an isolation region (28), laterally adjacent to said first impurity diffused layer (24 1 ) for electrically isolating said first layer (24↑).

Claim 4

A semiconductor device as set forth in claim 1, wherein said first impurity diffused layer (24 1 ) is formed on said insulation layer (26) and in said semiconductor substrate, forming a coplanar surface with said semiconductor substrate (20); and further comprising: a second insulation layer (30) formed to cover one part of the coplanar surface; a first electrode plate (32 1 ) disposed on said second insulation layer (30); a second electrode plate (32 2 ) electrically connected to said second impurity diffused layer (24 2 ); and an isolation region (28), laterally adjacent to said first impurity diffused layer (24 1 ), for electrically isolating said first layer (24↑); said fixed voltage supply means (V cc ) being electrically connected to said first electrode plate (32,) and said second electrode plate (32 2 ).

Claim 5

A semiconductor device as set forth in claim 3, wherein said first electrode plate (32↑), said second insulation layer (30), and said first impurity diffused layer (24 1 ) form a first capacitor, and said first impurity diffused layer (24↑), said insulation layer (26), and said second impurity diffused layer (24 2 ) form a second capacitor connected in parallel to said first capacitor.

Claim 6

A semiconductor device as set forth in claim 4, wherein said insulation layer (26) is formed between said first impurity diffused layer (24 1 ) and said second impurity diffused layer (24 2 ) and abuts said isolation region (28).

Claim 7

A semiconductor device as set forth in claim 5, wherein said first type of conductivity is a P-type conductivity and a positive voltage is operatively applied to said second impurity diffused layer (24 2 ).

Claim 8

A semiconductor device as set forth in claim 3, further comprising an MOS transistor (T i ) comprising: a third impurity diffused layer (3) having said second type of conductivity, forming one of a drain or a source on the coplanar surface of said ' semiconductor substrate and being separated from said first and second impurity diffused layers; a gate electrode (32 1 ) formed on said second insulation layer (30); and said first impurity diffused layer functioning as one of a source and a drain.

Claim 9

A semiconductor device as set forth in claim 7, wherein said first electrode plate (32↑), said second insulation layer (30) and said first impurity diffused layer (24 1 ) form a first capacitor, and said first impurity diffused layer (24 1 ), said insulation layer (26), and said second impurity diffused layer (24 2 ) form a second capacitor connected in parallel to said first capacitor.

Claim 10

A semiconductor device as set forth in claim 8, wherein said insulation layer (26) is formed between said first impurity diffused layer (24 1 and said second impurity diffused layer (24 2 ) and abuts said isolation region (28).

Claim 11

A semiconductor device as set forth in claim 9, wherein said MOS transistor and said first and second capacitors form a dynamic cell.

Claim 12

A semiconductor device as set forth in claim 10, wherein said first type of conductivity is a P-type conductivity and a positive voltage is applied to said second impurity diffused layer (24 2 ).

Claim 13

A semiconductor device as set forth in claim 11, wherein said gate electrode is connected to a word line and said third impurity diffused layer is connected to a bit line in the semiconductor device.