EP0083208A2 — A bias circuit for an emitter coupled logic circu…

Claim 1

Independent Claim 112 words

A bias circuit for providing a bias voltage to an output means (T 13 , T4) comprising: a first transistor (T 12 ) having an emitter, a base, and a collector, said base and said collector being connected to each other; a first reference-voltage terminal for providing a first reference voltage (VEE1) connected to said emitter; a constant-voltage node (N c ); an output end (0 1 ) connected to said base and said collector, for providing said bias voltage; and a first impedance means connected between said constant-voltage node and said output end, said bias voltage being applied to said output means (T 13 , T4) connected to said output end.

Claim 2

Dependent Claim 112 words

A bias circuit for providing a bias voltage to an output means (T 13 , T4) comprising: a first transistor (T 12 ) having an emitter, a base, and a collector, said base and said collector being connected to each other; a first reference-voltage terminal for providing a first reference voltage (VEE1) connected to said emitter; a constant-voltage node (N c ); an output end (0 1 ) connected to said base and said collector, for providing said bias voltage; and a first impedance means connected between said constant-voltage node and said output end, said bias voltage being applied to said output means (T 13 , T4) connected to said output end.

Claim 3

Dependent Claim 86 words

A bias circuit as set forth in claim 1, further comprising, between said constant-voltage node and said first reference-voltage terminal; a PN junction element having one end connected to said constant-voltage node, and another end; and a second transistor (T 10 ) having a base and a collector commonly connected to said other end of said PN junction element and having an emitter connected to said first reference-voltage terminal, the voltage at said constant-voltage node being determined by said PN junction element and said second transistor.

Claim 4

Dependent Claim 57 words

A bias circuit as set forth in claim 2 wherein said PN junction element comprises a third transistor (T11) having a conductivity opposite to the conductivity of said first transistor, said third transistor having an emitter connected to said constant-voltage node, a base connected to the base and the collector of said second transistor, and a collector.

Claim 5

Dependent Claim 26 words

A bias circuit as set forth in claim 3, wherein said collector of said third transistor is connected to said first reference-voltage terminal (V EE1 ).

Claim 6

Dependent Claim 45 words

A bias ciarcuit as set forth in claim 3, further comprising a second reference-voltage terminal for providing a second reference-voltage (VEE2) which is lower than the first reference voltage (V EEI ), the second refernce-voltage terminal being connected to said collector of said third trnasistor.

Claim 7

Dependent Claim 140 words

A logic circuit comprising an emitter coupled logic circuit including a bias output means for providing a bias voltage thereto and a bias circuit for providing a bias voltage to said bias output means, the bias circuit comprising: a first transistor (T 12 ) having an emitter, a base, and a collector, said base and said collector being connected to each other; a first reference-voltage terminal for providing a first reference voltage (V EE1 ) connected to said emitter; a constant-voltage node (N C ); an output end (O 1 ) connected to said base and said collector, for providing said bias voltage. and a first impedance means (R 13 ) connected between said constant-voltage node and said output end, said output end being connected to said bias output means ( T 13 ' T14) to provide said bias voltage.

Claim 8

Dependent Claim 140 words

A logic circuit comprising an emitter coupled logic circuit including a bias output means for providing a bias voltage thereto and a bias circuit for providing a bias voltage to said bias output means, the bias circuit comprising: a first transistor (T 12 ) having an emitter, a base, and a collector, said base and said collector being connected to each other; a first reference-voltage terminal for providing a first reference voltage (V EE1 ) connected to said emitter; a constant-voltage node (N C ); an output end (O 1 ) connected to said base and said collector, for providing said bias voltage. and a first impedance means (R 13 ) connected between said constant-voltage node and said output end, said output end being connected to said bias output means ( T 13 ' T14) to provide said bias voltage.

Claim 9

Dependent Claim 79 words

A logic circuit as set forth in claim 6, wherein said bias output means comprises a second transistor (T 13 ) having a base connected to said output end (O 1 ), an emitter connected to said first reference-voltage terminal, and a collector connected through a second impedance means (R 12 ) to a second reference-voltage terminal (V CC ), said collector of said second transistor providing a logicreference voltage (V BBl ) of the emitter coupled logic circuit.

Claim 10

Dependent Claim 64 words

A logic circuit as set forth in claim 6, wherein said bias output means comprises a third transistor (T 4 ) for providing a constant current for the emitter coupled logic circuit, the third transistor having a base connected to said output end (0 1 ), an emitter connected to said first eference-voltage terminal, and a collector through which said constant current is provided.

A bias circuit for an emitter coupled logic circuit

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