Electrically erasable programmable read only memory cell having a single transistor

Claim 2

A memory formed on a semiconductor comprising: A. an array of transistors comprising: (1) common source and drain diffusions of a first conductivity type extending in a plurality of parallel columns, (2) common insulated control electrodes extending over said parallel columns in a plurality of parallel rows; (3) a plurality of insulated floating gates juxtaposed between various pairs of adjacent ones of said source and drain diffusions and underlying respective ones of said control electrodes, (4) an insulating layer surrounding said floating gates including a plurality of thin tunneling regions between the source and floating gate of each transistor; B. means for reading including means for applying one voltage to a selected overlying control electrode and for applying a different voltage to the other ones of said overlying control electrodes, said different voltage being sufficient to turn off transistors having charged floating gates; C. means for erasing including: (1) means for applying a first voltage to the source diffusion of a selected one of said columns and a second voltage to the unselected source diffusions of the remaining ones of said columns, and (2) means for applying a third voltage to a selected one of said control electrodes and a fourth voltage to the remaining ones of said control electrodes; and D. means for writing including: (1) means for applying a fifth voltage to the source diffusion of a selected one of said columns and a sixth voltage to the unselected source diffusions of the remaining ones of said columns, and (2) means for applying a seventh voltage to a selected one of said control electrodes and an eighth voltage to the remaining ones of said control electrodes.

Claim 3

The memory of Claim 1 further comprising a well of conductivity type opposite to said sources and drains and containing said sources and drains, and means for controlling the potential of said well so as to prevent forward bias current flow between said well and any of said common source and drain diffusions.

Claim 4

The memory of Claim 1 wherein said reading means applies a positive voltage on the order of 5 volts to the control gates of selected transistors and a negative voltage on the order of -5 volts to the control gates of unselected transistors.

Claim 5

The memory of Claims 1 or 3 wherein said third and fifth voltages are about equal, said fourth and sixth voltages are about equal, said first and seventh voltages are about equal and said second and eighth voltages are about equal.

Claim 6

A memory formed on a semiconductive layer of a first conductivity type, comprising: A. a well region of a second conductivity type formed in said semiconductive layer; B. a plurality of transistors formed in said well region, comprising: (1) common source and drain diffusions of said first conductivity type extending in a plurality of parallel columns, (2) a plurality of common insulated control electrodes extending in a plurality of parallel rows over said common source and drain diffusions; (3) a plurality of insulated floating gates juxtaposed between adjacent source and drain columns, overlying said well region under said insulated control electrodes and separated therefrom by an insulating layer having a plurality of tunneling regions therein underlying said plurality of floating gates, C. means for reading including means for applying a particular voltage to a selected one of said control electrodes and applying a different voltage to the remaining control electrodes; D. means for charging a selected one of said floating gates by applying a first voltage to the corresponding source diffusion and applying a second voltage to the remaining source diffusions while applying a third voltage to the selected one of said overlying control electrodes and applying a fourth voltage to the remaining ones of said overlying control electrodes, wherein the sum of said first and third voltages is sufficient to cause charge to tunnel between said well region and said selected one floating gate and wherein the sum of any other two of said first, second, third and fourth voltages is insufficient to cause charge to tunnel between a corresponding source and floating gate; E. means for discharging a selected one of said floating gates by applying voltages as in Step D above, except that said first and third and said second and fourth voltages are interchanged, respectively; and F. means for controlling the potential of said well region so as to prevent a forward bias current between said well region and any of said source and drain diffusions.

Claim 7

A memory formed on a semiconductive layer of a first conductivity type, comprising: A. a well region of a second conductivity type formed in said semiconductive layer; B. a plurality of transistors formed in said well region, comprising: (1) common source and drain diffusions of said first conductivity type extending in a plurality of parallel columns, (2) a plurality of common insulated control electrodes extending in a plurality of parallel rows over said common source and drain diffusions; (3) a plurality of insulated floating gates juxtaposed between adjacent source and drain columns, overlying said well region under said insulated control electrodes and separated therefrom by an insulating layer having a plurality of tunneling regions therein underlying said plurality of floating gates, C. means for reading including means for applying a particular voltage to a selected one of said control electrodes and applying a different voltage to the remaining control electrodes; D. means for charging a selected one of said floating gates by applying a first voltage to the corresponding source diffusion and applying a second voltage to the remaining source diffusions while applying a third voltage to the selected one of said overlying control electrodes and applying a fourth voltage to the remaining ones of said overlying control electrodes, wherein the sum of said first and third voltages is sufficient to cause charge to tunnel between said well region and said selected one floating gate and wherein the sum of any other two of said first, second, third and fourth voltages is insufficient to cause charge to tunnel between a corresponding source and floating gate; E. means for discharging a selected one of said floating gates by applying voltages as in Step D above, except that said first and third and said second and fourth voltages are interchanged, respectively; and F. means for controlling the potential of said well region so as to prevent a forward bias current between said well region and any of said source and drain diffusions.

Claim 8

The memory of Claim 5 wherein said particular voltage and said different voltage of said reading means are on the order of +5 volts and -5 volts respectively, and wherein said first and second voltages and said third and fourth voltages of said charging and discharging means are, alternatively, on the order of -12 volts, 0 volts, +5 volts, -5 volts, respectively, or +5 volts, -5 volts, -12 volts and 0 volts, respectively.

Claim 9

The memory of Claims 5 or 6 wherein said well region potential controlling means operates in synchronism with said charging and discharging means so as to maintain a zero or a reverse bias potential between said well region and all of said common source and drain diffusions.

Claim 12

The method of Claim 8 , further comprising the steps of forming a complementary well region in said semiconductor, said well region containing said source and drain columns, and controlling the potential of said well region so as to prevent a forward bias current between said well region and any of said common source and drain diffusions.

Claim 13

The method of Claim 8 wherein the sum of said first and third voltages, or of said fifth and seventh voltages, is sufficient to cause tunneling of charge through said tunneling region.