Memory circuit

Claim 2

A memory circuit comprising first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells, a bus line, a sense amplifier having first and second input nodes, first switching means coupled between said first bit line and said first input node, means for connecting said second bit line to said second input node, second switching means coupled between said bus line and said second input node, said first bit line and said first input node being kept disconnected with said bus line, and means for controlling said first switching means so as to make said first switching means non-conducting till a state of said sense amplifier is established by a write signal transmitted from said bus line through said second switching means to said second input node during write operation period and make said first switching means conducting after the state of said sense amplifier is established.

Claim 3

The memory circuit according to claim 1, in which each of said first switching means and said second switching means includes a field effect transistor.

Claim 4

The memory circuit according to claim 1, in which said sense amplifier includes a control node, a first field effect transistor coupled between said first input node and said control node and having a gate coupled to said second input node, and a second field effect transistor coupled between said second input node and said control node.

Claim 5

The memory circuit according to claim 1, further comprising an output amplifier coupled to said bus line.

Claim 6

A memory circuit comprising first and second memory arrays disposed adjacently to each other, first and second bus lines associated to said first and second memory arrays; each of said first and second memory arrays including a plurality of sense amplifiers each having first and second input nodes, a plural pairs of bit lines, each pair of said bit lines being associated with each of said sense amplifiers, a plurality of first switching means each coupled between the first input node of each sense amplifier and one of the associated pair of bit lines, a plurality of second switching means each coupled between the second input node of each sense amplifier and the associated one of said first and second bus lines, a plurality of word lines intersecting with said bit lines, and a plurality of memory cells; means for selectively enabling one of said second switching means thereby to establish a signal path between one of said bus lines and the second input node of the selected sense amplifier; and means for controlling said first switching means to make the first switching means at a high impedance state till a state of the associated sense amplifier is determined in accordance with a signal applied to the second input node thereof through the signal path established by the associated second switching means and then to make the first switching means at a low impedance state after the state of the sense amplifier is established.

Claim 7

A memory circuit comprising first and second memory arrays disposed adjacently to each other, first and second bus lines associated to said first and second memory arrays; each of said first and second memory arrays including a plurality of sense amplifiers each having first and second input nodes, a plural pairs of bit lines, each pair of said bit lines being associated with each of said sense amplifiers, a plurality of first switching means each coupled between the first input node of each sense amplifier and one of the associated pair of bit lines, a plurality of second switching means each coupled between the second input node of each sense amplifier and the associated one of said first and second bus lines, a plurality of word lines intersecting with said bit lines, and a plurality of memory cells; means for selectively enabling one of said second switching means thereby to establish a signal path between one of said bus lines and the second input node of the selected sense amplifier; and means for controlling said first switching means to make the first switching means at a high impedance state till a state of the associated sense amplifier is determined in accordance with a signal applied to the second input node thereof through the signal path established by the associated second switching means and then to make the first switching means at a low impedance state after the state of the sense amplifier is established.

Claim 8

The memory circuit according to claim 6, further comprising a pair of reference signal generators coupled to said pair of bus lines.

Claim 9

The memory circuit according to claim 6, further comprising a main amplifier coupled to said pair of bus lines.

Claim 10

A memory circuit comprising first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells, a sense amplifier having first and second input node, a first field effect transistor coupled between said first bit line and said first input node, a second field effect transistor coupled between said second bit line and said second input node, a bus line, a third field effect transistor coupled between said bus line and said second bit line, means for operatively conducting said third transistor thereby to provide an electrical path between said bus line and said second input node, means for controlling a conductance of said second field effect transistor, and mean for controlling said first transistor so as to operatively isolate said first bit line from said first input node.

Claim 11

A memory circuit comprising first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells, a sense amplifier having first and second input node, a first field effect transistor coupled between said first bit line and said first input node, a second field effect transistor coupled between said second bit line and said second input node, a bus line, a third field effect transistor coupled between said bus line and said second bit line, means for operatively conducting said third transistor thereby to provide an electrical path between said bus line and said second input node, means for controlling a conductance of said second field effect transistor, and mean for controlling said first transistor so as to operatively isolate said first bit line from said first input node.

Claim 12

The memory circuit according to claim 9, further comprising a main amplifier having a first input terminal coupled to said bus line and a second input terminal and a reference signal generator coupled to said second input terminal and operatively generating a reference signal.