EP0083088A2
Expired / Lapsed
EP
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Method of producing field effect transistors having very short channel length
Assignee: International Business Machines Corp
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Filing: 1982-12-27
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Granted: —
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Expires: 2002-12-27
Abstract
Abstract Methods for producing field effect transistor devices having very short channel length are described. A surface isolation pattern (12) in a semiconductor substrate (10) isolates device regions of the semiconductor within the substrate from one another. An insulating layer (16) destined to be the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern (12). Then a first polycrystalline silicon layer (20) is formed thereover. A masking layer (22) such as silicon dioxide is then formed upon the first polycrystalline layer. The multilayer structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls. A sub- micrometer thickness conductive layer (26') is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer (26') portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices.
Inventors
- 👤 Jacob Riseman
- 👤 Paul Ja-Min Tsang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:17
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
267 words
Method of producing field effect transistors having very short channel length, on the basis of a monocrystalline silicon substrate (10) covered by a first silicon dioxide coating (16), characterized by the steps of forming a first polycrystalline silicon layer (20) on said silicon dioxide coating (16); forming a silicon nitride layer (22) over said first polycrystalline silicon layer; removing portions of said silicon nitride layer and said first polycrystalline silicon layer down to said silicon dioxide coating to produce openings having substantially vertical sidewalls on the remaining said silicon nitride layer (22) and polycrystalline silicon layer (20); thermally oxidizing the exposed sidewalls of said first polycrystalline silicon layer (20) to produce a silicon dioxide layer (24) thereon; depositing a conductive layer (26) over the various substantially vertical and substantially horizontal surfaces; anisotropically etching said conductive layer (26) to substantially remove all of said layer from the horizontal surfaces while leaving said conductive layer (26') on said vertical surfaces; oxidizing to form a silicon dioxide layer (26) upon the remaining said conductive layer (26'); removing the remaining said silicon nitride layer (22) and said first polycrystalline silicon layer (20) to define the gate regions of said field effect transistors by the remaining conductive layer (26') and form the gate electrodes from it; ion implanting a conductivity imparting impurity into said silicon substrate (10) to form the source/drain regions (36) using the said remaining conductive layer (26') and the silicon dioxide layers (24, 28) covering it as the mask of the channel of the field effect transistors; and electrically contacting said source/drain regions (36) and said gate electrodes (26').
Claim 2
Dependent Claim
267 words
Method of producing field effect transistors having very short channel length, on the basis of a monocrystalline silicon substrate (10) covered by a first silicon dioxide coating (16), characterized by the steps of forming a first polycrystalline silicon layer (20) on said silicon dioxide coating (16); forming a silicon nitride layer (22) over said first polycrystalline silicon layer; removing portions of said silicon nitride layer and said first polycrystalline silicon layer down to said silicon dioxide coating to produce openings having substantially vertical sidewalls on the remaining said silicon nitride layer (22) and polycrystalline silicon layer (20); thermally oxidizing the exposed sidewalls of said first polycrystalline silicon layer (20) to produce a silicon dioxide layer (24) thereon; depositing a conductive layer (26) over the various substantially vertical and substantially horizontal surfaces; anisotropically etching said conductive layer (26) to substantially remove all of said layer from the horizontal surfaces while leaving said conductive layer (26') on said vertical surfaces; oxidizing to form a silicon dioxide layer (26) upon the remaining said conductive layer (26'); removing the remaining said silicon nitride layer (22) and said first polycrystalline silicon layer (20) to define the gate regions of said field effect transistors by the remaining conductive layer (26') and form the gate electrodes from it; ion implanting a conductivity imparting impurity into said silicon substrate (10) to form the source/drain regions (36) using the said remaining conductive layer (26') and the silicon dioxide layers (24, 28) covering it as the mask of the channel of the field effect transistors; and electrically contacting said source/drain regions (36) and said gate electrodes (26').
Claim 3
Dependent Claim
212 words
Method of producing field effect transistors having very short channel length, on the basis of a monocrystalline silicon substrate (10) covered by a first silicon dioxide coating (16), characterized by the steps of forming a first polycrystalline silicon layer (50) upon said first silicon dioxide coating (16); forming a second layer (52) of silicon dioxide upon said first polycrystalline silicon layer (50); removing portions of said second layer (52) of silicon dioxide to produce openings having substantially vertical sidewalls on the remaining said second layer of silicon dioxide; depositing a conductive layer (54) over the various substantially vertical and substantially horizontal surfaces; anisotropically etching said conductive layer (54) to substantially remove all of said conductive layer from the horizontal surfaces while leaving said conductive layer on said vertical surfaces; removing the remaining said second layer (52) of silicon dioxide; forming a sidewall insulating layer (64) upon the said substantially vertical surfaces of said conductive layer; ion implanting conductivity imparting impurities into said silicon substrate (10) to form the source/drain regions (66) using the remaining conductive layer (54) and said sidewall insulating layer (64) as the mask of each channel; and electrically contacting said source/drain regions, the remaining said conductive layer areas (54) acting as the gate electrodes for said field effect transistors.
Claim 4
Dependent Claim
212 words
Method of producing field effect transistors having very short channel length, on the basis of a monocrystalline silicon substrate (10) covered by a first silicon dioxide coating (16), characterized by the steps of forming a first polycrystalline silicon layer (50) upon said first silicon dioxide coating (16); forming a second layer (52) of silicon dioxide upon said first polycrystalline silicon layer (50); removing portions of said second layer (52) of silicon dioxide to produce openings having substantially vertical sidewalls on the remaining said second layer of silicon dioxide; depositing a conductive layer (54) over the various substantially vertical and substantially horizontal surfaces; anisotropically etching said conductive layer (54) to substantially remove all of said conductive layer from the horizontal surfaces while leaving said conductive layer on said vertical surfaces; removing the remaining said second layer (52) of silicon dioxide; forming a sidewall insulating layer (64) upon the said substantially vertical surfaces of said conductive layer; ion implanting conductivity imparting impurities into said silicon substrate (10) to form the source/drain regions (66) using the remaining conductive layer (54) and said sidewall insulating layer (64) as the mask of each channel; and electrically contacting said source/drain regions, the remaining said conductive layer areas (54) acting as the gate electrodes for said field effect transistors.
Claim 5
Dependent Claim
23 words
A method in accordance with claim 1 or 2, characterized in that said conductive layer (26, 54) is a second polycrystalline silicon layer.
Claim 6
Dependent Claim
27 words
A method in accordance with claim 1 or 2, characterized in that said conductive layer (26, 54) is a combination layer of polycrystalline silicon and metal silicide.
Claim 7
Dependent Claim
21 words
A method in accordance with claim 1 or 2, characterized in that said conductive layer (26, 54) is a metal silicide.
Claim 8
Dependent Claim
49 words
A method in accordance with claim 3, characterized in that said second polycrystalline silicon layer (26, 54) has a thickness of between about 200 to 950 nanometers which produces field effect transistors with said very short channel length of substantially the same dimension as said second polycrystalline silicon layer.
Claim 9
Dependent Claim
51 words
A method in accordance with claim 3, characterized in that said second polycrystalline silicon layer (26, 54) is N+ and is doped by an ion implantation process after its deposition using between about 1 x 10 15 to 1 x 10 16 ions/cm 2 at between about 30 to 100 keV.
Claim 10
Dependent Claim
86 words
A method in accordance with claim 1 wherein a lightly doped source/drain region (32) is formed, characterized by the steps of forming an N- region in said substrate (10) using said remaining conductive layer (26') having said silicon dioxide layers (24, 28) thereon as a mask; forming.an additional sidewall silicon dioxide layer (34) upon the said substantially vertical surfaces of said remaining conductive layer (26') covered by silicon dioxide layer (24, 28); and completing the source/drain structure by ion implanting of N+ type conductivity imparting impurities.
Claim 11
Dependent Claim
38 words
A method in accordance with claim 8, characterized in that said sidewall silicon dioxide layer (34) has a thickness of between about 200 to 750 nanometers.. which delineates said lightly doped source/drain region (32) by such an amount.
Claim 12
Dependent Claim
71 words
A method in accordance with claim 8, characterized in that said step of forming an N- region is effected by ion implantation using 1 x 10 12 to 1 x 10 13 i ons/cm 2 at 40 to 100 keV and said step of ion implanting of N+ type conductivity imparting impurity is effected using 1 x 10 15 to 1 x 10 16 ions/cm 2 and 30 to 100 keV.
Claim 13
Dependent Claim
78 words
A method in accordance with claim 1, characterized in that regions on the surface of said monocrystalline silicon substrate (10) are isolated from each other by a surface isolation pattern (12) in said substrate, and said first polycrystalline silicon layer (20) is patterned by said step of removing portions of it, so as to overlap said isolation pattern and partially cover two of said regions whereby single field effect transistors are formed in each of said two regions.
Claim 14
Dependent Claim
63 words
A method in accordance with claim 2 wherein a lightly doped source/drain region (62) is formed, characterized by the steps of forming an N- region in said substrate using said remaining conductive layer (54) as a mask just prior to the formation of said sidewall insulating layer (64) and completing thereafter the source/drain structure by ion implantation of N+ type conductivity imparting impurities.
Claim 15
Dependent Claim
37 words
A method in accordance with claim 12, characterized in that said sidewall insulating layer (64) has a thickness of between about 200 to 750 nanometers which delineates said lightly doped source/drain region (62) by such an amount.
Claim 16
Dependent Claim
76 words
A method in accordance with claim 12, characterized in that said step of forming an N- region is effected by ion implantation using between about 1 x 10 12 to 1 x 10 13 ions/cm 2 at between about 40 to 100 keV and said step of ion implanting of N+ type impurities is effected using between about 1 x 10 15 to 1 x 10 16 ions/cm 2 and between about 40 to 80 keV.
Claim 17
Dependent Claim
78 words
A method in accordance with claim 2, characterized in that regions on the surface of said monocrystalline substrate (10) are isolated from each other by a surface isolation pattern (12) in said substrate, and said second layer (52) of silicon dioxide is patterned by said step of removing portions of it, so as to overlap said isolation pattern and partially cover two of said regions whereby single field effect transistors are formed in each of said two regions.
References Cited (Backward Citations)
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