Apparatus and method for CMOS multistaged dynamic logic circuit

Claim 3

The method of Claim 2 characterized in that said step of providing said changing means comprises the step of: providing in said changing means in said first one of said logic structures of said first conductivity type, a means responsive to said evaluation signal and a predetermined input signal for changing said first one of said logic structures from its precharged state to its active state; and providing in said changing means in the remaining ones of said plurality of logic structures of said first conductivity type and said logic structures of said second conductivity type, means responsive to a predetermined output received from the preceding logic structure coupled thereto and a predetermined input signal for changing said remaining ones of said plurality of logic structures of said first conductivity type and said logic structure of said second conductivity type from their precharged state to their active state.

Claim 4

A dynamic logic circuit characterized by: means in each one of a plurality of logic structures of a first and a second conductivity type for precharging said logic structure; means for changing said logic structures from a precharged state to an active state; means for coupling said plurality of logic structures, other than a first one of said logic structures, of said first conductivity type to an output of one of said plurality of logic structures of said second conductivity type so that said logic structures of said first and said second conductivity types are coupled alternately in series; means, in said changing means of said first one of said logic structures of said first conductivity type, responsive to an evaluation signal for changing said first one of said logic structures of said first conductivity type and succeeding logic structures of said first and said second conductivity type from their precharged state to their active state.

Claim 5

A dynamic logic circuit characterized by: means in each one of a plurality of logic structures of a first and a second conductivity type for precharging said logic structure; means for changing said logic structures from a precharged state to an active state; means for coupling said plurality of logic structures, other than a first one of said logic structures, of said first conductivity type to an output of one of said plurality of logic structures of said second conductivity type so that said logic structures of said first and said second conductivity types are coupled alternately in series; means, in said changing means of said first one of said logic structures of said first conductivity type, responsive to an evaluation signal for changing said first one of said logic structures of said first conductivity type and succeeding logic structures of said first and said second conductivity type from their precharged state to their active state.

Claim 6

The circuit of claim 3 characterized in that said changing means in said first one of said logic structures of said first conductivity type comprises a means responsive to said evaluation signal and predetermined input signal for changing said first one of said logic structures from its precharged state to its active state; and said changing means in the remaining ones of said plurality of logic structures of said first conductivity type and said logic structures of said second conductivity type, comprise means responsive to a predetermined output received from the preceding logic structure coupled thereto and a predetermined input signal for changing said remaining ones of said plurality of logic structures of said first conductivity type and said logic structure of said second conductivity type from their precharged state to their active state.

Claim 7

The circuit of claim 3 characterized in that a first logic structure of said plurality of logic structures is of a first conductivity type and has a first input means for receiving a first input signal, a second input means for receiving an evaluation signal, a means for precharging said first logic structure to a precharged state, means responsive to said first input signal and said evaluation signal for changing the state of said structure from said precharged state to an active state, an ouput, and means responsive to a change of state of said first logic structure from said precharge state to said active state for providing an output signal on said output of said first logic structure; and in that a second logic structure of said plurality of logic structures is of a second conductivity type and has an input means for receiving said output signal, means separate from said input of said second logic structure for precharging said second logic structure to a precharged state, means for coupling said output of said first logic structure to said second input of said second logic structure, means responsive to said input signal received by said second logic structure for changing the state of said second logic structure from said precharged state to an active state; an output; and means responsive to a change of state of said second logic structure from said precharged state to said active state for providing an output signal on said output of said second logic structure.

Claim 8

The circuit of claim 5 characterized in that one of said first and said second logic structures is a P-channel logic structure and the other of said logic structures is an N-channel logic structure.

Claim 9

The circuit of Claim 5 or 6 characterized in that said output signal on said output of said second logic structure comprises a third evaluation signal, and comprising: a third logic structure of said first conductivity type having an input means for receiving an input signal, for receiving said evaluation signal from said second logic structure, means separate from said input means of said third logic strucutre for precharging said third logic structure to a precharged state, means for coupling said output of said second logic structure to said input means of said third logic structure; means responsive to said input signal received by said third logic structure for changing the state of said third logic structure from said precharged state to an active state; and means responsive to a change of state of said third logic structure from said precharged state to said active state for providing an output signal on said output of said third logic structure.

Claim 10

The circuit Claim 5 or 7 characterized in that said first and third logic structures are P-channel logic structures and said second logic structure is an N-channel logic structure.

Claim 11

The circuit of Claim 5 or 6, 7 or 8 characterized in that charging means comprises means for precharging each of said logic structures simultaneously.

Claim 12

The circuit of Claim 7 characterized in that said first and third logic structures are N-channel logic structures and said second logic structure is a P-channel logic structure.

Claim 13

The circuit of any one of Claims 5-10 characterized in that said first input means of predetermined ones of said first and said input means of predetermined ones of said second plurality of logic circuits comprises means for coupling a plurality of inputs to each of said predetermined ones of said structures.