EP0082567A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
TTL to CMOS input buffer
Assignee: Motorola Solutions Inc
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Filing: 1982-12-14
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Granted: —
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Expires: 2002-12-14
Abstract
Abstract A TTL to CMOS input buffer (36) accomplishes buffering a TTL signal to a CMOS signal without requiring current flow through a CMOS input inverter in a static condition by introducing a reference voltage to match the lowest level of a logic "1" of the TTL signal. The input inverter (40) has a P channel transistor (50) which, by having a source at the reference voltage, does not turn on when the TTL signal is at the lowest level of a logic "1". The reference voltage is selected to be less than the lowest level of a logic "1" minus the threshold voltage of the P channel transistor (50).
Inventors
- 👤 Glenn Eric Noufer
- 👤 William James Donoghue
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 19:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
187 words
A TTL to CMOS input buffer for providing an output signal in a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode coupled to a reference voltage, and a second current electrode for providing a first output; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; and reference voltage generator means coupled to a second power supply terminal and the first power supply terminal for providing a CMOS reference voltage at a voltage which is no closer to the first power supply voltage than the TTL reference voltage minus the threshold voltage of the first transistor of the first conductivity type.
Claim 2
Dependent Claim
187 words
A TTL to CMOS input buffer for providing an output signal in a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode coupled to a reference voltage, and a second current electrode for providing a first output; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; and reference voltage generator means coupled to a second power supply terminal and the first power supply terminal for providing a CMOS reference voltage at a voltage which is no closer to the first power supply voltage than the TTL reference voltage minus the threshold voltage of the first transistor of the first conductivity type.
Claim 3
Dependent Claim
317 words
The TTL to CMOS input buffer of claim 1 further comprising: a second transistor of the first conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the CMOS reference voltage, and a second current electrode; a second transistor of the second conductivity type having a control electrode coupled to the control electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply voltage, and a second current electrode coupled to the second current electrode of the second transistor of the first conductivity type; a third transistor of the second conductivity type having a control electrode coupled to the second current electrode of the second transistor of the first conductivity type, a first current electrode coupled to the first power supply terminal, and a second current electrode; a third transistor of the first conductivity type having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the second current electrode of the third transistor of the second conductivity type, and a control electrode; a fourth transistor of the second conductivity type having a control electrode coupled to the second current electrode of the first transistor of the first conductivity type, a first current electrode coupled to the first power supply terminal, and a second current electrode for providing a second output coupled to the control electrode of the third transistor of the first conductivity type; and a fourth transistor of the first conductivity type having a control electrode coupled to the second current electrode of the third transistor of the second conductivity type, a first current electrode coupled to the second power supply terminal, and a sencond current electrode coupled to the second current electrode of the fourth transistor of the second conductivity type.
References Cited (Backward Citations)
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