Method of manufacturing a semiconductor device comprising dielectric isolation regions

Claim 3

A method according to claim 1, wherein said semiconductor layer (101, 138) is a semiconductor substrate.

Claim 4

A method according to claim 1, wherein said semiconductor layer (128) is an epitaxial layer which is formed on a semiconductor substrate of the conductivity type same to that of said epitaxial layer.

Claim 5

A method according to claim 1, wherein said semiconductor layer (132) is an epitaxial layer formed on an insulating substrate (131).

Claim 6

A method according to claim 1, wherein said thin layer (105, 130) comprises a material which is selectively etched with respect to said first and second mask patterns (103, 106', 133').

Claim 7

A method according to claim 1 or 5, wherein said first mask pattern (103) comprises polycrystalline silicon, said thin layer (105, 136) comprises SiO 2 , and said second mask pattern (106') comprises a photoresist.

Claim 8

A method according to claim 1 or 5, wherein said first mask pattern comprises polycrystalline silicon, said thin layer comprises Si3N4, and said second mask pattern comprises a photoresist.

Claim 9

A method according to claim 1 or 5, wherein said first mask pattern comprises Si0 2 , said thin layer comprises polycrystalline silicon, and said second mask pattern comprises a photoresist.

Claim 10

A method according to claim 1 or 5, wherein said first mask pattern comprises SiO 2 , said thin layer comprises polycrystalline silicon, and said second mask pattern comprises Si 3 N 4 .

Claim 11

A method according to claim 1 or 6, wherein said first mask pattern (103) which comprises polycrystalline silicon is thermally oxidized to form said thin layer (105) of Si0 2 on said at least side surfaces of said first mask pattern (103).

Claim 12

A method according to claim 1, 6, 7 or 8, wherein said second mask pattern (106') is formed by forming a photoresist film (106) to cover the entire surface and by etching back said photoresist film (106).

Claim 13

A method according to claim 2 or 3, wherein after said trench (108) is formed, a carrier killer layer is formed in a bottom of said trench (108) in said semiconductor layer by ion-implantation.

Claim 14

A method according to claim 12, wherein said carrier killer layer is formed by ion-implanting a material selected from the group consisting of an oxide, carbon and aurum.

Claim 15

A method according to claim 1, wherein said element isolation region (111) is formed by burying SiO 2 ( 110 ) in said trench (108).

Claim 16

A method according to claim 1, wherein said element isolation region (111) is formed by burying polycrystalline silicon (136) in said trench (108) through an Si0 2 film (134).

Claim 17

A method according to claim 4, wherein a bottom of said element isolation region (111) reaches a surface of said insulating substrate (131).

Claim 18

A method according to claim 1, 2 or 3, wherein a well region (112) which has a conductivity type opposite to that of said semiconductor layer (101, 128) and which has a depth smaller than a depth of said element isolation region is formed in a portion of said semiconductor layer (101, 128) isolated by said element isolation region (111) by the steps of: forming said first mask pattern (103) on said semiconductor layer (101, 128) through said SiO 2 film (102); ion-implanting an impurity of the conductivity type opposite to that of said semiconductor layer (101, 128) in said semiconductor layer (101, 128), using said first mask pattern, to form an ion injection layer (104) of a conductivity type opposite to that of said semiconductor layer (101, 128); forming said thin layer (105, 130) on said at least side surfaces of said first mask pattern (103); selectively forming said second mask pattern (106') on said portion of said SiO 2 film (102) between said portions of said thin layer (105, 130) formed on said side surfaces of said first mask pattern (103); selectively etching said portions of said thin layer (105, 130) formed on said at least side surfaces of said first mask pattern (103), and said portions of said Si0 2 film (102) under said portions of said thin layer (105, 130) formed on said side surfaces of said first mask pattern (103), using said first and second mask patterns (103, 106'); selectively etching an exposed portion of said semiconductor layer (101, 128) to form said trench (108); forming said element isolation region by burying said insulating material (110) in said trench (108); and annealing to diffuse said impurity_from said ion injection layer (104).

Claim 19

A method according to claim 3, wherein a well region (112) of a conductivity type opposite to that of said epitaxial layer (128) is formed in a portion of said epitaxial layer (128) which is surrounded by a buried layer (129) of the conductivity type same to that of said epitaxial layer (128) and said element isolation region (111) by the steps of: forming said buried layer (129) of a highly concentrated impurity of the conductivity type same to that of said epitaxial layer (128) in a prospective well region at an interface between said semiconductor substrate (101) and said epitaxial layer (128); forming said first mask pattern (103) on said epitaxial layer (128) through said Si0 2 film (102); ion-implanting an impurity of the conductivity type opposite to that of said epitaxial layer (128) in said epitaxial layer (128), using said first mask pattern (103), to form an ion injection layer (104) of the conductivity type opposite to that of said epitaxial layer (128); forming said thin layer (130) on said at least side surfaces of said first mask pattern (103); selectively forming said second mask pattern (106') on said portion of said Si0 2 film (102) located between said portions of said thin layer (130) formed on said side surfaces of said first mask pattern (103); selectively etching said portions of said thin layer (130) formed on said at least side surfaces of said first mask pattern (103), and said portions of said Sio 2 film (102) under said portions of said thin layer (130) formed on said side surfaces of said first mask pattern (103), using said first and second mask patterns (103, 106'); selectively etching an exposed portion of said epitaxial layer (128) to form said trench (108); burying said insulating material (110) in said trench (108) to form said element isolation region (111) whose bottom reaches at least said buried layer (129); and performing annealing to diffuse said impurity from said ion injection layer (104).