Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
135 words
A synchronous data bus system comprising a bus (14) extending between a master controller (.20) and peripheral controllers (28), the bus including data/address lines (32), and a clock line (54) distributing a fixed period clock signal which synchronizes data transfers, and the controllers including registers (60,62; 116,118) for storing information to be transmitted and information received, characterised in that the bus (14) also includes a hold line (56) on which a receiving controller may assert a hold signal so long as it is not ready to receive information on the data/address lines, and in that each controller (20; 28) includes means (64; 92) responsive to a hold signal on the hold line to cause information to be transmitted to remain stored and to be transmitted on a clock signal following termination of the hold signal.
Claim 2
Dependent Claim
135 words
A synchronous data bus system comprising a bus (14) extending between a master controller (.20) and peripheral controllers (28), the bus including data/address lines (32), and a clock line (54) distributing a fixed period clock signal which synchronizes data transfers, and the controllers including registers (60,62; 116,118) for storing information to be transmitted and information received, characterised in that the bus (14) also includes a hold line (56) on which a receiving controller may assert a hold signal so long as it is not ready to receive information on the data/address lines, and in that each controller (20; 28) includes means (64; 92) responsive to a hold signal on the hold line to cause information to be transmitted to remain stored and to be transmitted on a clock signal following termination of the hold signal.
Claim 3
Dependent Claim
115 words
A bus system according to claim 1, characterised in that the bus (14) includes a plurality of request lines (42) corresponding to the peripheral controllers (28) respectively, whereby each peripheral controller may request access for transfer of information, and a ready line (44) for conducting a ready signal (RDY) from the master controller (20) to the peripheral controllers (28), in that the master controller (20) is responsive to a request signal (RQ) on any request line (42) to provide the ready signal (RDY) when the master controller is ready to transfer information, and in that ' each peripheral controller (28) includes to initiate transfer of information when that controller is providing the request for access.
Claim 4
Dependent Claim
159 words
A bus system according to claiml or 2, wherein the information is transferred in blocks of one or more words to or from a main memory (18) associated with the master controller, characterised in that the bus (14) also includes word count lines (38) for transferring a number specifying the words required in a block, in that each peripheral controller is operative to initiate a block transfer by transferring a starting address to the address/ data lines (32) and to transfer the said number to the word count lines, in that the master controller includes a first register (62) for storing the starting address received on the address/data lines, a second register (68) for storing the said number received on the word count lines, and in that the master controller is arranged to transfer the block by repeatedly transferring a word and incrementing the first register (62) as many times as the number transferred to the second register (68).
Claim 5
Dependent Claim
141 words
A bus system according to claim 1, 2 or 3, characterised in that the bus (14) includes parity line means (46,48), an error line (52) and an abort line (50), in that each controller (20,28) includes parity circuits which transfer parity signals to the parity line means when transferring information to the address/data lines (32), in that the master controller (20) comprises means responsive to information and parity signals received from a peripheral controller to provide an error signal on the error line when a parity error is detected, and means responsive to an abort signal on the abort line to terminate a current transfer of information, and in that each peripheral controller comprises means responsive to information and parity signals received from the master controller to provide an abort signal on the abort line when a parity error is detected.