EP0081396A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microwave field effect transistor
Assignee: National Aeronautics and Space Administration
•
Filing: 1982-10-18
•
Granted: —
•
Expires: 2002-10-18
Abstract
Abstract Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segment of the source electrodes. The gate and drain electrodes include inactive pads remote from the active segments thereof. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes establish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.
Inventors
- 👤 Chung Huang Ho
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:17
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/60; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/257; H10D64/27; H10D64/311; H10D64/411
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
218 words
A microwave field effect transistor having electrodes substantially matched to external input and output networks comprising a metal ground plane layer, dielectric means, a gallium arsenide active region, substan- tailly co-planar spaced source, gate and drain electrodes having active and inactive segments respectively contacting the active region and the dielectric means, the active segment of the gate electrode being located between the active segments of the source and drain electrodes, one of the drain and source electrodes being connected to the ground plane layer, the inactive segments of the gate electrode and-of the other electrode being respectively connected directly to the input and output networks, the active region having an impedance between the gate electrode and the one electrode substantially less than the impedance of the input network, the active region having an impedance between the other electrode and the ground plane substantially less than the impedance of the output network, the geometry and spacing of the electrodes establishing parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the active region and between the active region and the output network, the lengths of the inactive segments of the gate and the other electrodes having lengths less than a wavelength of a microwave signal applied to the gate electrode by the input network.
Claim 2
Dependent Claim
218 words
A microwave field effect transistor having electrodes substantially matched to external input and output networks comprising a metal ground plane layer, dielectric means, a gallium arsenide active region, substan- tailly co-planar spaced source, gate and drain electrodes having active and inactive segments respectively contacting the active region and the dielectric means, the active segment of the gate electrode being located between the active segments of the source and drain electrodes, one of the drain and source electrodes being connected to the ground plane layer, the inactive segments of the gate electrode and-of the other electrode being respectively connected directly to the input and output networks, the active region having an impedance between the gate electrode and the one electrode substantially less than the impedance of the input network, the active region having an impedance between the other electrode and the ground plane substantially less than the impedance of the output network, the geometry and spacing of the electrodes establishing parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the active region and between the active region and the output network, the lengths of the inactive segments of the gate and the other electrodes having lengths less than a wavelength of a microwave signal applied to the gate electrode by the input network.
Claim 3
Dependent Claim
51 words
The transistor of claim 1 wherein N of said field effect transistors are provided on the ground plane layer; where N is an integer greater than one, the inactive segments of the N gate electrodes and of the other electrodes being connected in parallel to the input and output networks, respectively.
Claim 4
Dependent Claim
141 words
The transistor of claim 2 wherein the inactive segments of the gate electrodes of the N transistors are connected together to a first single inactive metal strip, and the inactive segments of the other electrode are connected to a second single inactive metal strip, first and second metal posts respectively extending from the first and second strips to provide contacts directly to the input and output networks, N third metal posts directly connected to the one electrode of each of the N transistors and to the ground plane, respectively, said first, second and third posts extending in the same direction from the active region toward the ground plane, the input and output networks being metal strips on a dielectric layer carried by the ground plane, the metal strips and the ground plane being insulated from each other by the dielectric layer.
Claim 5
Dependent Claim
55 words
The transistor of claim 3 wherein the electrodes are carried by a first face of the active region so they face the dielectric layer and the substrate, the active region including a second face opposite from the first face and remote from the electrodes, whereby the field effect transistors are arranged in a flip-chip configuration.
Claim 6
Dependent Claim
37 words
The transistor of claims 2, 3 or 4 wherein the active segment of the gate electrodes for the N transistors comprises a single continuous stripe connected at different points to the inactive segments of the N transistors.
Claim 7
Dependent Claim
205 words
A microwave field effect transistor having electrodes adapted to be connected to external input and output networks comprising a metal ground plane layer, dielectric layer means on the ground plane layer, an active region on the dielectric layer means, N field effect devices being formed on the active layer, where N is an integer greater than one, each of the devices including: co-planar, spaced source, drain and gate electrodes on a face of the active region; each pair of adjacent devices sharing the same source electrodes; each pair of adjacent devices sharing the same drain electrodes; whereby the gate electrode of device K is between the drain and source electrodes of device K, the drain electrodes of devices K and (K-1) are shared, and the source electrodes of devices K and (K+l) are shared, where K=2... (N-1) ; a common gate pad for the N gate electrodes; a common pad for another electrode of each of the N devices; the remaining electrodes of the N devices being connected to the ground plane; the gate electrodes for the N devices being a continuous stripe extending between adjacent ones of the devices and connected at different points to the common gate pad for the N gate electrodes.
Claim 8
Dependent Claim
205 words
A microwave field effect transistor having electrodes adapted to be connected to external input and output networks comprising a metal ground plane layer, dielectric layer means on the ground plane layer, an active region on the dielectric layer means, N field effect devices being formed on the active layer, where N is an integer greater than one, each of the devices including: co-planar, spaced source, drain and gate electrodes on a face of the active region; each pair of adjacent devices sharing the same source electrodes; each pair of adjacent devices sharing the same drain electrodes; whereby the gate electrode of device K is between the drain and source electrodes of device K, the drain electrodes of devices K and (K-1) are shared, and the source electrodes of devices K and (K+l) are shared, where K=2... (N-1) ; a common gate pad for the N gate electrodes; a common pad for another electrode of each of the N devices; the remaining electrodes of the N devices being connected to the ground plane; the gate electrodes for the N devices being a continuous stripe extending between adjacent ones of the devices and connected at different points to the common gate pad for the N gate electrodes.
Claim 9
Dependent Claim
37 words
The transistor of claim 6 wherein the source electrodes of devices K and (K+l) are formed as parts of first and second fingers interdigitated with a third finger forming the drain electrodes of devices K and (K+l).
Claim 10
Dependent Claim
166 words
The transistor of claim 7 wherein each electrode of each device includes an active segment contacting the active region and an inactive segment that does not overlay the active region, wherein the inactive segments of the gate electrodes of the N transistors are connected together to a first single inactive metal strip, and the inactive segments of the other electrode are connected to a second single inactive metal strip, first and second metal posts respectively extending from the first and second strips to provide contacts directly to the input and output networks, N third metal posts directly connected to the one electrode of each of the N transistors and to the ground plane, respectively, said first, second and third posts extending in the same direction from the active region toward the ground plane, the input and output networks being metal strips on a dielectric layer carried by the ground plane, the metal strips and the ground plane being insulated from each other by the dielectric layer.
Claim 11
Dependent Claim
55 words
_The transistor of claim 8 wherein the electrodes are carried by a first face of the active region so they face the dielectric layer and the substrate, the active region including a second face opposite from the first face and remote from the electrodes, whereby the field effect transistors are arranged in a flip-chip configuration.
Claim 12
Dependent Claim
123 words
The transistor of claims 6, 7, 8 or 9 wherein the active region has an impedance between the gate electrode and the one electrode substantially less than the impedance of the input network, the active region having an impedance between the other electrode and the ground plane substantially less than the impedance of the output network, the geometry and spacing of the electrodes establishing parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the active region and between the active region and the output network, the lengths of the inactive segments of the gate and the other electrodes having lengths less than a wavelength of a microwave signal applied to the gate electrode by the input network.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.