EP0080901A2
Expired / Lapsed
EP
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Data processing apparatus
Assignee: Bull HN Information Systems Inc
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Filing: 1982-12-01
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Granted: —
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Expires: 2002-12-01
Abstract
Abstract A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.
Inventors
- 👤 William E. Woods
- 👤 Philip E. Stanley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 16:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/30; G06F9/30181; G06F9/30192; G06F9/26; G06F9/262; G06F9/268
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
274 words
A central processor unit (CPU) for executing instructions, and including a control store means having locations for storing a plurality of microwords and generating a plurality of control store signals for each of said plurality of microwords for controlling the operation of said CPU; characterized in that one of said instructions includes a first word and a second word, said first word including an operation code field for identifying the instructions as one which the CPU will execute, and an escape code field for identifying a class of instruction including extended integer instructions (EII) and commercial instruction processor (CIP) instructions, said second word including a data type field for identifying an operand type and an address syllable field which in conjunction with said escape code field generates an effective address, and by register means (38,76) responsive to a first plurality of said control store signals for storing signals representative of said data type field; read only memory means (44-2) responsive to a first operation code signal (FREGOO), a first control store signal (PLUPOL) and a second control store signal (MISC7B), and said data type field signals (FPMR04-07) for generating a plurality of operand size signals (ODSIZ1,2,4, ODARRD); and multiplexer means (30-2) responsive to a second plurality of said control store signald (CRTC13-15) and said plurality of operand size signals for generating a test signal (TCGRP2) representative of a selected one of said plurality of operand size signals, said control store means being responsive to said test signal for branching to said location storing the next of said one of said plurality of microwords for generating a next of said plurality of control store signals.
Claim 2
Dependent Claim
274 words
A central processor unit (CPU) for executing instructions, and including a control store means having locations for storing a plurality of microwords and generating a plurality of control store signals for each of said plurality of microwords for controlling the operation of said CPU; characterized in that one of said instructions includes a first word and a second word, said first word including an operation code field for identifying the instructions as one which the CPU will execute, and an escape code field for identifying a class of instruction including extended integer instructions (EII) and commercial instruction processor (CIP) instructions, said second word including a data type field for identifying an operand type and an address syllable field which in conjunction with said escape code field generates an effective address, and by register means (38,76) responsive to a first plurality of said control store signals for storing signals representative of said data type field; read only memory means (44-2) responsive to a first operation code signal (FREGOO), a first control store signal (PLUPOL) and a second control store signal (MISC7B), and said data type field signals (FPMR04-07) for generating a plurality of operand size signals (ODSIZ1,2,4, ODARRD); and multiplexer means (30-2) responsive to a second plurality of said control store signald (CRTC13-15) and said plurality of operand size signals for generating a test signal (TCGRP2) representative of a selected one of said plurality of operand size signals, said control store means being responsive to said test signal for branching to said location storing the next of said one of said plurality of microwords for generating a next of said plurality of control store signals.
Claim 3
Dependent Claim
132 words
The processor of Claim 1, characterized in that said read only means comprises: a read only memory (44-2) having a plurality of input address terminals and an enable terminal, said enable terminal being responsive to a third control store signal (MISC6B) indicative of said EII and said CIP instruction for enabling said read only memory; said input address terminals being responsive to said data type field signals and said first operation code signal in a first state indicative of an EII operand for generating said plurality of operand size signals representative of said EII operand, and responsive to said first operation code signal in a second state indicative of a CIP instruction operand and said data type field signals for generating said plurality of operand signals representative of said CIP instruction operand.
Claim 4
Dependent Claim
56 words
The processor of Claim 2, characterized in that said read only memory input address terminals are further responsive to a fourth control store signal (MEMADR) indicative of whether said operand is stored in said memory subsystem or in a plurality of registers, and responsive to said data type field signals for generating said operand size signals.
Claim 5
Dependent Claim
74 words
The processor of Claim 3, characterized in that said read only memory input address terminals are further responsive to said fourth control store indicating that the operand is stored in the plurality of registers, a fifth control store signal (FPMR08) in a first or second state and said data type field signals for generating said operand size signals indicative of the size of said operand being stored in a first or second register respectively.
References Cited (Backward Citations)
No citation records indexed.
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