EP0080890A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interface circuit for subsystem controller
Assignee: Unisys Corp
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Filing: 1982-11-30
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Granted: —
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Expires: 2002-11-30
Abstract
Abstract An Interface Circuit Card for interfacing a subsystem-controller (called a Network Support Processor) in a data communications system to a main host computer and to a plurality of line support processors which service data communications lines to remote terminals. The Interface Circuit Card provides a data link interface logic circuit (DLI) for connecting the master processor of the Network Support Processor to a distribution control card which contacts the main host system computer. The Interface Circuit Card also provides a message level interface (MLI) logic circuit which connects the master processor to another distribution control card for connection to a line support processor and also to buses which connect to a master memory control card for accessing a shared memory means.
Inventors
- 👤 Craig Weaver Harris
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 15:46
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
195 words
In a data communications system where a peripheral-controller controls data transfer operations between main memory of a main host computer and a plurality of line communications processors connected to peripheral terminals, said peripheral-controller including processor means, controller-memory means and an Interface Circuit to said main host computer and said line communications processors, and wherein said processor means uses PUT and GET instructions to control operation of said Interface Circuit, the Interface Circuit comprising: (a) a first interface logic means for providing data transfer between said controller-memory means and main memory of said host computer; (b) a second interface logic means for providing data transfer between said line communications processor and said controller-memory means: (c) first connection means connecting said first interface logic means to said main host computer; (d) second connection means connecting said second interface logic means to a selected said line communications processor; (e) bus means including: (el) an 1/0 bus connecting said processor means to said first and second interface logic means; (e2) a memory address bus connecting said second interface logic means to said controller-memory means; (e3) a controller-memory output data bus connecting said controller-memory to said second interface logic means.
Claim 2
Dependent Claim
195 words
In a data communications system where a peripheral-controller controls data transfer operations between main memory of a main host computer and a plurality of line communications processors connected to peripheral terminals, said peripheral-controller including processor means, controller-memory means and an Interface Circuit to said main host computer and said line communications processors, and wherein said processor means uses PUT and GET instructions to control operation of said Interface Circuit, the Interface Circuit comprising: (a) a first interface logic means for providing data transfer between said controller-memory means and main memory of said host computer; (b) a second interface logic means for providing data transfer between said line communications processor and said controller-memory means: (c) first connection means connecting said first interface logic means to said main host computer; (d) second connection means connecting said second interface logic means to a selected said line communications processor; (e) bus means including: (el) an 1/0 bus connecting said processor means to said first and second interface logic means; (e2) a memory address bus connecting said second interface logic means to said controller-memory means; (e3) a controller-memory output data bus connecting said controller-memory to said second interface logic means.
Claim 3
Dependent Claim
77 words
The Interface Circuit of claim 1 wherein said first (PLI) interface logic means includes: (2a) latching register means for receiving data from said main host computer via said first connection means; (2b) FIFO register means for temporarily storing data received by said latching register means; (2c) internal 1/0 bus means for carrying data from said FIFO register means to said controller-memory means; (2d) counter means to count the number of data words transferred to said controller-memory means.
Claim 4
Dependent Claim
30 words
The Interface Circuit of claim 2 wherein a PUT instruction received from said processor means is used to load a word from main host memory into said FIFO register means.
Claim 5
Dependent Claim
30 words
The Interface Circuit of claim 2 wherein a GET instruction received from said processor means is used to transfer a word from said FIFO register means to said controller-memory means.
Claim 6
Dependent Claim
42 words
The Interface Circuit of claim 2 wherein said first (DLI) interface logic means further includes: (5a) PROM sequencing means for generating control signals to: said FIFO register means, said second (MLI) interface logic means, said host computer, and said line communications processor.
Claim 7
Dependent Claim
42 words
The Interface Circuit of claim 5 wherein said PROM sequencing means includes: (6a) a sequence start-address register for receiving start-address data from said processor means; (6b) a control PROM initiated by said start-address register and providing control signals for data transfer operations.
Claim 8
Dependent Claim
44 words
The Interface Circuit of claim 6 wherein said sequencing means further includes: (7a) an output register receiving control signals from said control PROM, said output register providing next-address signals to said control PROM and control signals to said first and second interface logic means.
Claim 9
Dependent Claim
47 words
The Interface Circuit of claim 1 wherein said second (MLI) interface logic means includes: (8a) connection means linking said processor means to said controller-memory means; (8b) control means for generating control signals; (8c) data transfer means for normal mode data transfer or direct memory access mode transfer.
Claim 10
Dependent Claim
38 words
The Interface Circuit of claim 8 wherein said connection means includes: (9a) means for addressing said controller-memory means; (9b) means for counting the number of words transferred; (9c) means for setting the number of words to be transferred.
Claim 11
Dependent Claim
61 words
The Interface Circuit of claim 8 wherein said control means includes: (10a) an MLI Control Register for receiving instructions from said processing means and setting control signals in a MLI Control Logic Unit; (lOb) an MLI Control Logic Unit for enabling addresses to be transmitted to said controller-memory means and for providing status signals and control data to said processor means.
Claim 12
Dependent Claim
64 words
The Interface Circuit of claim 8 wherein said data transfer means includes: (lla) a data register for receiving control words and data words from said processor means; (llb) driver means for transmitting data from said data register to a selected line communications processor or to a data receiver; (llc) a data receiver for routing data from said line communications processor to said controller-memory means.
References Cited (Backward Citations)
No citation records indexed.
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