Memory mapping unit

Claim 2

A memory mapping unit used to map any 2 K sized memory board to any 2 N address boundary, for a 2 M memory space having an M bit address buss connected in parallel to each memory board, the 2 K memory board can range in size from N S ≤ K ≤ M, each memory mapping unit is associated with a particular memory board and produces a board enable command when the address carried by the address buss identifies a location on the board memory, comprising: a base address register for storing the 2's complement of the base address of the memory board; an adding means connected to said base address register and the address buss for adding the value in the base address register with significant bits of the memory address; a board size mask register for masking out bits which are not useful for a particular board size; a first logical means connected to said adding means and said board size register for masking the bits in said adding means with said corresponding bits in said board size mask register; and, a second logical means connected to said first logical means which will produce a board enable command.

Claim 3

A memory mapping unit used to map a 2 K size memory board to any 2 N address boundary, for a 2 M memory space having a M bit address buss connected in parallel to each memory board, the 2 K memory board can range in size from N ≤ K < M, each memory board mapping unit is associated with a particular memory board and produces a board enable command when the address carried by the address buss identifies the location on the memory board, comprising: a base address register containing (M - N) bits for storing the 2's complement of the base address of the memory board; an adding means connected to said base address register and the address buss for adding the value of the base address register with the upper (M - N) bits of the memory address; a board size mask register containing (M - N) bits for masking out bits which are not useful for a particular board size such that for a 2 K board, the first (K - N) least significant bits in said board size register should be "zero" and the upper (N - K) bits should be "one"; first logical means connected to said adding means and said board size mask register for performing an AND operation on each bit in said adding means with its corresponding bit position in said board size mask register; and, a second logical means connected to said first logical means for a NOR operation on the output from said first logical means and producing a board enable command, which turns on the memory board when the memory address identifier is located on the board.

Claim 4

A memory mapping unit used to map a 2 K size memory board to any 2 N address boundary, for a 2 M memory space having a M bit address buss connected in parallel to each memory board, the 2 K memory board can range in size from N ≤ K < M, each memory board mapping unit is associated with a particular memory board and produces a board enable command when the address carried by the address buss identifies the location on the memory board, comprising: a base address register containing (M - N) bits for storing the 2's complement of the base address of the memory board; an adding means connected to said base address register and the address buss for adding the value of the base address register with the upper (M - N) bits of the memory address; a board size mask register containing (M - N) bits for masking out bits which are not useful for a particular board size such that for a 2 K board, the first (K - N) least significant bits in said board size register should be "zero" and the upper (N - K) bits should be "one"; first logical means connected to said adding means and said board size mask register for performing an AND operation on each bit in said adding means with its corresponding bit position in said board size mask register; and, a second logical means connected to said first logical means for a NOR operation on the output from said first logical means and producing a board enable command, which turns on the memory board when the memory address identifier is located on the board.

Claim 5

3 . The apparatus according to claim 1 or 2 in which said base address register and said board size mask register are software loaded.

Claim 6

The apparatus of claim 2 in which said first logical means contains (M - N) AND gates each connected to one bit from said board size mask register and a corresponding bit from said adding means.

Claim 7

The apparatus of claim 2 in which said second logical means is a NOR gate with (M - N) ports connected to each output of said first logical means.

Claim 8

6 . A memory mapping unit is used to map any 2K sized memory board to any 2 N address boundary, for a 2 M memory space having a M bit address buss connected in parallel to each memory board, the 2 K memory board can range in size from N < K i M, each memory mapping unit is associated with a particular memory board and produces a board enable command when the address carried by the address buss identifies the location on the memory board, comprising: a base address containing (M - N) bits, which is software loaded, with the 2's complement base address of the memory board; a (M - N ) bit adder connected to said base address register and the upper (M - N) bits of the address buss; a board sized mask register, which is software loaded with (M -N) bits, such that for a 2 K board, the first (K - N) least significant bits are "zero" and the upper (M - N) bits are "one"; a plurality of (M - N) AND gates, each connected to one bit from said board size mask register and a corresponding bit from said (M - N) bit adder; and, a NOR gate connected to the output of each of said plurality of (M - N) AND circuits and producing as its output a board enable command.

Claim 9

6 . A memory mapping unit is used to map any 2K sized memory board to any 2 N address boundary, for a 2 M memory space having a M bit address buss connected in parallel to each memory board, the 2 K memory board can range in size from N < K i M, each memory mapping unit is associated with a particular memory board and produces a board enable command when the address carried by the address buss identifies the location on the memory board, comprising: a base address containing (M - N) bits, which is software loaded, with the 2's complement base address of the memory board; a (M - N ) bit adder connected to said base address register and the upper (M - N) bits of the address buss; a board sized mask register, which is software loaded with (M -N) bits, such that for a 2 K board, the first (K - N) least significant bits are "zero" and the upper (M - N) bits are "one"; a plurality of (M - N) AND gates, each connected to one bit from said board size mask register and a corresponding bit from said (M - N) bit adder; and, a NOR gate connected to the output of each of said plurality of (M - N) AND circuits and producing as its output a board enable command.