EP0080280A1
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EP
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A synchronous video detector circuit using phase-locked loop
Assignee: Panasonic Holdings Corp
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Filing: 1982-11-02
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Granted: —
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Expires: 2002-11-02
Abstract
Abstract in a synchronous video detector circuit using a phase-locked loop (PLL; 13,14,15,16), the synchronous detection of a video IF signal is effected with a synchronous carrier signal reproduced by the PLL including a voltage-controlled oscillator (15). Each of a phase comparator (13) of the PLL and a synchronous video detector (18) has its input terminal connected to an output terminal of a video IF amplifier (11) by untuned coupling (17, 17'), and arranged on the output side of the synchronous video detector (18) is a phase-locked mode detector (19) for detecting that the PLL is in its phase-locked mode. The phase-locked mode detector (19) is adapted to control the band width of a low-pass filter (14) of the PLL in either a narrow band mode or a wide band mode and the low-pass filter (14) is controlled to operate in the narrow band mode only when the PLL is in the phase-locked mode of operation. The black and white noise included in the output signal of the synchronous video detector (18) are both cancelled by a noise cancellation circuit (20) including a black noise detector (21) for pulse noise calcellation purposes.
Inventors
- 👤 Mitsuo Isobe
- 👤 Tetsuo Kutsuki
- 👤 Namio Yamaguchi
- 👤 Toshihide Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:54
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/455; H03; H03B; H03B5/00; H03B5/08; H03B5/12; H03B5/1206; H03B5/1209; H03B5/1231; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
317 words
A synchronous video detector circuit using a phase-locked loop comprising: voltage-controlled oscillator means (15, 16) for receiving an intermediate frequency signal from a video IF amplifier (11) and for generating first and second oscillation output signals having a phase difference of approximately T r/2 (rad) relative to each other; first multiplier means (18) for receiving said intermediate frequency signal amplified to a given amplitude level by said video IF amplifier (11) and said first oscillation output signal; second multiplier means (13) for receiving said intermediate frequency signal amplified to a given amplitude by said video IF amplifier (11) and said second oscillation output signal; coupling means (17, 17') of a type substantially untuned for supplying the output signal of said video IF amplifier (11) to said first and second multiplier means (18, 13), respectively; phase-locked mode detecting means (19) for receiving an output signal component of said first multiplier means (18) to detect the presence of a video signal output; and low-pass filter means (14) for generating substantially a dc component of an output signal from said second multiplier means (13) as a control signal to said oscillator means (15, 16), at least the time constant of said filter means (14) being adapted to be selected from or changed over to selected one of a plurality of values, whereby the time constant of said low-pase filter means (14) is increased in value to provide a narrow band characteristic which satisfactorily attenuates a vertical scanning frequency component when said phase-locked mode detecting means (19) detects that a phase-locked loop (PLL) including said voltage-controlled oscillator means (15, 16), said second multiplier means (13) and said low-pass filter means (14) is in a phase-locked mode of operation and said time constant is decreased in value to provide a wider band characteristic than said narrow band characteristic when said phase-locked loop (PLL) is in any other mode than said phase-locked mode.
Claim 2
Dependent Claim
317 words
A synchronous video detector circuit using a phase-locked loop comprising: voltage-controlled oscillator means (15, 16) for receiving an intermediate frequency signal from a video IF amplifier (11) and for generating first and second oscillation output signals having a phase difference of approximately T r/2 (rad) relative to each other; first multiplier means (18) for receiving said intermediate frequency signal amplified to a given amplitude level by said video IF amplifier (11) and said first oscillation output signal; second multiplier means (13) for receiving said intermediate frequency signal amplified to a given amplitude by said video IF amplifier (11) and said second oscillation output signal; coupling means (17, 17') of a type substantially untuned for supplying the output signal of said video IF amplifier (11) to said first and second multiplier means (18, 13), respectively; phase-locked mode detecting means (19) for receiving an output signal component of said first multiplier means (18) to detect the presence of a video signal output; and low-pass filter means (14) for generating substantially a dc component of an output signal from said second multiplier means (13) as a control signal to said oscillator means (15, 16), at least the time constant of said filter means (14) being adapted to be selected from or changed over to selected one of a plurality of values, whereby the time constant of said low-pase filter means (14) is increased in value to provide a narrow band characteristic which satisfactorily attenuates a vertical scanning frequency component when said phase-locked mode detecting means (19) detects that a phase-locked loop (PLL) including said voltage-controlled oscillator means (15, 16), said second multiplier means (13) and said low-pass filter means (14) is in a phase-locked mode of operation and said time constant is decreased in value to provide a wider band characteristic than said narrow band characteristic when said phase-locked loop (PLL) is in any other mode than said phase-locked mode.
Claim 3
Dependent Claim
47 words
A synchronous video detector circuit according to Claim 1, wherein said first multiplier means (18) receives a composite signal comprising a video IF signal and a sound IF signal, and wherein an intercarrier sound signal is obtained from an output signal of said first multiplier means (18).
Claim 4
Dependent Claim
70 words
A synchronous video detector circuit according to Claim 1, wherein said low-pass filter means (14) comprises at least a capacitor (142), a first resistor (143) and a second resistor (144) connected in series between a signal output terminal of said low-pass filter means (14) and a ground potential or a given reference potential, and wherein said second resistor (144) is disposed to be short-circuited thereacross by semiconductor switching means (200).
Claim 5
Dependent Claim
18 words
A synchronous video detector circuit according to Claim 3, wherein said semiconductor switching means (200) comprises a transistor.
Claim 6
Dependent Claim
78 words
A synchronous video detector circuit according to Claim 1, further comprising noise cancellation means (20) comprising a black noise detector (21) for detecting black noise components in the output video signal from said first multiplier means (18), and a pulse-width stretcher (23) for increasing the duration of an output noise pulse from said black noise detector (21), whereby at least white noise in said video signal is removed by said output noise pulse from said pulse-width stretcher (23).
Claim 7
Dependent Claim
31 words
A synchronous video detector circuit according to Claim 5, wherein both black noise and white noise in said video signal are removed the output noise pulse from said pulse-width stretcher (23).
Claim 8
Dependent Claim
55 words
A synchronous video detector circuit according to Claim 5, wherein said pulse-width stretcher (23) comprises at least a first transistor (227) of emitter follower configuration, and a second transistor (226) connected as a diode in series with a base electrode of said first transistor (227) to receive the base current thereof as a forward current.
Claim 9
Dependent Claim
39 words
A synchronous video detector circuit according to Claim 7, wherein said black noise detector (21) and said pulse-width stretcher (23) are formed in a single integrated circuit chip, and wherein said second transistor (226) comprises a lateral PNP transistor.
Claim 10
Dependent Claim
198 words
A synchronous video detector circuit according to Claim 1, wherein said voltage-controlled oscillator means (15, 16) comprises a voltage-controlled oscillator circuit comprising at least a plurality of amplifying means (153, 154), a load circuit (159, 160) connected between given electrodes of said amplifying means (153, 154) and forming a load, feedback means for feeding signal components generated at output terminals of said load circuit (159, 160) back to signal input electrodes of said amplifying means (153, 154) to apply positive feedback thereto, variable current source circuit means (151, 152, 161, 162, 163, 164, E 61 E7) having a voltage-controlled input terminal to vary a bias current to said amplifying means (153, 154), variable voltage source circuit means (155, 156) for detecting a current change in said variable current source circuit means and converting the same into a voltage change to generate an output in the same direction as said current change, and bias means (157, 158) for supplying the output voltage of said variable voltage source circuit means (155, 156) to said amplifying means (153, 154) and thereby maintaining the dc bias levels at the output electrodes of said amplifying means (153, 154) at a substantially constant value.
Claim 11
Dependent Claim
78 words
A synchronous video detector circuit according to Claim 9, wherein said load circuit (159, 160) comprises a parallel resonant circuit load comprising at least an inductance element for setting a free- running oscillation frequency, and wherein said bias means (157, 158) comprises a pair of bias resistors each having one end thereof connected to one end of said load and the other end thereof connected to an output terminal of said variable voltage source circuit means (155, 156).
Claim 12
Dependent Claim
119 words
ll. A synchronous video detector circuit according to Claim 9, wherein said variable current source circuit means (151, 152, 161, 162, 163, 164, E6, E 7 ) comprises a transistor pair (151, 152) having one of base electrodes as a voltage-controlled terminal and emitter electrodes connected to each other directly or through given resistors (161, 162), one of the collectors of said transistor pair (151, 152) being connected so as to vary the bias current to said amplifying means (153, 154) and the other of said collector electrodes being connected to a constant reference voltage source (E 5 ) through a resistor (155) with a dc bias at the junction point thereof being outputted through a buffer transistor (156).
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