Analog-to-digital converter

Claim 2

An analog to digital converter comprising: a reference input; an analog input; scaled array of binary weighted capacitors; a comparator with first and second comparator inputs and to produce an output upon detection of a voltage difference between said first and second inputs; said second input connected to the scaled array; a first switching means connected between said reference input and the scaled array; a scaled capacitor connected to the first comparator input and scaled proportionally to the array of binary weighted capacitors; a second switching means connected between said reference input and said first comparator input and scaled proportionally to the size of said first switching means in relation to the ratio of the size of the scaled capacitor to the size of the scaled array; a third switching means connected between said analog input and said scaled array; register means; switch control means for controlling said first, second and third switching means by switching off said first and second switching means before switching off said third switching means; means to digitally approximate the analog input by selective successive comparisons of the scaled array capacitors to the reference input and to store the digital approximation in the register means.

Claim 3

An analog to digital converter comprising: a reference input; an analog input; a capacitive array of binary weighted capacitors; a series connected resistor array; a least significant bit capacitor equivalent to the smallest capacitor in the capacitor array and connected to said resistor array and together connected in parallel to said capacitor array; a comparator with first and second comparator inputs and an output to signify the existence of a voltage difference between the inputs, said second input connected to said capacitive array and said least significant bit capacitor; a reference capacitor connected to the first comparator input; switching means to connect the reference input to the first comparator input and to connect said analog input to said capacitive array; supplemental charge circuitry connected in parallel to said capacitive array for adjusting charge stored in said capacitive array; controller means connected to said comparator output, said switching means and said supplemental charge circuitry to adjust the charge stored in each of the binary weighted capacitors to the specified binary weight and to digitally approximate the analog input by successive selective comparisons of the binary weighted capacitors with charge adjustments to the reference input; register means connected to said control means to store the digital approximation.

Claim 4

An analog to digital converter comprising: a reference input; an analog input; a capacitive array of binary weighted capacitors; a series connected resistor array; a least significant bit capacitor equivalent to the smallest capacitor in the capacitor array and connected to said resistor array and together connected in parallel to said capacitor array; a comparator with first and second comparator inputs and an output to signify the existence of a voltage difference between the inputs, said second input connected to said capacitive array and said least significant bit capacitor; a reference capacitor connected to the first comparator input; switching means to connect the reference input to the first comparator input and to connect said analog input to said capacitive array; supplemental charge circuitry connected in parallel to said capacitive array for adjusting charge stored in said capacitive array; controller means connected to said comparator output, said switching means and said supplemental charge circuitry to adjust the charge stored in each of the binary weighted capacitors to the specified binary weight and to digitally approximate the analog input by successive selective comparisons of the binary weighted capacitors with charge adjustments to the reference input; register means connected to said control means to store the digital approximation.

Claim 5

A comparator comprising: a plurality of differential amplifiers connected in cascade to determine the existence of a voltage difference between a first and second input signal and to provide amplification of said voltage difference, output means connected to the final cascaded differential amplifier to output a signal upon the occurrence of a specific input voltage difference, a plurality of offset correction voltage circuits connected in cascade and each connected to one of each of said differential amplifiers to provide offset voltage correction to each of said differential amplifiers to compensate for device mismatching internal to said differential amplifiers.

Claim 6

A comparator comprising: a plurality of differential amplifiers connected in cascade to determine the existence of a voltage difference between a first and second input signal and to provide amplification of said voltage difference, output means connected to the final cascaded differential amplifier to output a signal upon the occurrence of a specific input voltage difference, a plurality of offset correction voltage circuits connected in cascade and each connected to one of each of said differential amplifiers to provide offset voltage correction to each of said differential amplifiers to compensate for device mismatching internal to said differential amplifiers.

Claim 7

An analog to digital converter comprising: a reference input; an analog input; a charge array of binary weighted capacitors; a series connected resistor array; a least significant bit capacitor equivalent to the smallest capacitors in the binary weighted charge array and connected to said resistor array and together connected in parallel to said charge array; a comparator with first and second comparator inputs and an output to signify the existence of a voltage difference between the inputs, said second input connected to said charge array and said least significant bit capacitor; a reference capacitor connected to the first comparator input; switching means to connect the reference input to the first comparator input and to connect said analog input to said charge array; controller means connected to said comparator output and said switching means to determine the most significant bits of a digital approximation of the analog input by Claim 4 continued successive selective comparison of the charge array capacitors to the reference input and to determine the least significant bits of the digital approximation by comparison of the selected charge array capacitors with the least significant bit capacitor in series with successive selective registors in said resistor array; register means connected to said control means to store the digital approximation.