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EP0077737A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Low capacitance field effect transistor

Assignee: Fairchild Semiconductor Corp
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Filing: 1982-10-19
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Granted: —
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Expires: 2002-10-19
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Abstract

Abstract A compact field effect transistor having extremely low source/drain to substrate capacitance is disclosed, together with a method of fabricating it. The source 27 and drain 25 regions of the FET are fabricated on an underlying layer of insulating material 12, typically silicon dioxide, while the gate region including a channel 24, is fabricated directly on the semiconductor substrate 10. The source/drain 27/25 and gate 24 regions are all simultaneously formed by deposition of a single layer of epitaxial silicon 21. In this manner a monocrystalline silicon gate region 24 is created with polycrystalline silicon source/drain regions 27/25. The different rate of growth of silicon dioxide over monocrystalline 24 and polycrystalline silicon 27/25 is utilized to create the gate oxide, while an overlying layer of doped polycrystalline silicon 30 serves as the gate electrode. The source/drain regions are typically doped by an impurity diffused from a layer of phosphorous glass deposited between the insulating material and the source/drain regions.

Inventors

  • 👤 Madhukar B. Vora

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 21:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0278; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/40; H10P; H10P14/00; H10P14/20; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/65; H10P14/6502

Claims Analysis

Total Claims: 34
Claim 1
Independent Claim 136 words
A method of fabricating an integrated circuit transistor structure characterized by: forming a first layer of insulating material over first and second spaced apart regions of a semiconductor substrate, the first and the second regions being separated by an intervening region of the substrate; depositing a layer of semiconductor material over the layer of insulating material and the intervening region; introducing a first conductivity type impurity into that portion of the layer of semiconductor material overlying the intervening region and introducing an opposite conductivity type impurity into that portion of the layer of semiconductor material overlying the layer of insulating material; forming a second layer of insulating material over the layer of semiconductor material; and fabricating an electrically conductive region over at least that portion of the second layer of insulating material overlying the intervening region.
Claim 2
Independent Claim 136 words
A method of fabricating an integrated circuit transistor structure characterized by: forming a first layer of insulating material over first and second spaced apart regions of a semiconductor substrate, the first and the second regions being separated by an intervening region of the substrate; depositing a layer of semiconductor material over the layer of insulating material and the intervening region; introducing a first conductivity type impurity into that portion of the layer of semiconductor material overlying the intervening region and introducing an opposite conductivity type impurity into that portion of the layer of semiconductor material overlying the layer of insulating material; forming a second layer of insulating material over the layer of semiconductor material; and fabricating an electrically conductive region over at least that portion of the second layer of insulating material overlying the intervening region.
Claim 3
Dependent Claim 39 words
The method of claim 1 characterized by the step of fabricating a third layer of insulating material over the first and second spaced apart regions prior to the step of depositing a layer of selected conductivity type semiconductor material.
Claim 4
Dependent Claim 22 words
The method of claim 2 characterized in that the third layer of insulating material comprises a source of opposite conductivity type impurity.
Claim 5
Dependent Claim 22 words
The method of claim 2 or 3 characterized in that the third layer of insulating material comprises P 2 O 5 .
Claim 6
Independent Claim 24 words
The method of any previous claim characterized in that the step of forming a first layer of insulating material comprises oxidizing the semiconductor substrate.
Claim 7
Independent Claim 26 words
The method of any previous claim characterized in that the step of forming a second layer of insulating material comprises oxidizing the layer of semiconductor material.
Claim 8
Dependent Claim 32 words
The method of claim 6 characterized in that the layer of semiconductor material oxidizes more rapidly over the first and second spaced apart regions than over the intervening region of the substrate.
Claim 9
Independent Claim 44 words
The method of any one of claims 2-7 characterized in that the step of fabricating an electrically conductive region comprises: depositing a layer of polycrystalline silicon; introducing impurities into the layer of polycrystalline silicon; and removing undesired regions of the layer of polycrystalline silicon.
Claim 10
Independent Claim 37 words
The method of any previous claim characterized in that a step of depositing an electrically conductive layer on the first layer of insulating material is performed following the step of forming a first layer of insulating material.
Claim 11
Dependent Claim 26 words
The method of claim 9 characterized in that a step of depositing a layer of polycrystalline silicon follows the step of depositing an electrically conductive layer.
Claim 12
Independent Claim 106 words
A method of fabricating an integrated circuit transistor structure characterized by: forming first and second spaced apart regions of oxidized semiconductor material overlaid by at least one selected layer on a semiconductor substrate; depositing a layer of semiconductor material over the substrate and the at least one selected layer to thereby create regions of polycrystalline semiconductor material over the at least one selected layer and a region of monocrystalline semiconductor material over the substrate; oxidizing the layer of semiconductor material; and forming an electrically conductive region of material over at least that portion of the oxidized layer of semiconductor material formed on the monocrystalline semiconductor material.
Claim 13
Independent Claim 106 words
A method of fabricating an integrated circuit transistor structure characterized by: forming first and second spaced apart regions of oxidized semiconductor material overlaid by at least one selected layer on a semiconductor substrate; depositing a layer of semiconductor material over the substrate and the at least one selected layer to thereby create regions of polycrystalline semiconductor material over the at least one selected layer and a region of monocrystalline semiconductor material over the substrate; oxidizing the layer of semiconductor material; and forming an electrically conductive region of material over at least that portion of the oxidized layer of semiconductor material formed on the monocrystalline semiconductor material.
Claim 14
Dependent Claim 24 words
The method of claim 11 characterized in that the at least one selected layer comprises a first layer as a source of impurity dopant.
Claim 15
Dependent Claim 21 words
The method of claim 12 characterized in that the first layer provides impurity dopants for the overlying layer of semiconductor material.
Claim 16
Dependent Claim 25 words
The method of claim 13 characterized in that that at least one layer includes a second layer comprising electrically conductive material beneath the first layer.
Claim 17
Dependent Claim 95 words
An integrated circuit transistor structure characterized by: a semiconductor substrate; first and second spaced apart regions of insulating material disposed on the substrate, the first and second regions being separated by an intervening region of the substrate; a layer of semiconductor material disposed across the first and the second regions and across the intervening region of the substrate; a layer of insulating material disposed across the surface of the layer of semiconductor material; and an electrode overlying at least that portion of the layer of insulating material which overlies the intervening region of the substrate.
Claim 18
Dependent Claim 95 words
An integrated circuit transistor structure characterized by: a semiconductor substrate; first and second spaced apart regions of insulating material disposed on the substrate, the first and second regions being separated by an intervening region of the substrate; a layer of semiconductor material disposed across the first and the second regions and across the intervening region of the substrate; a layer of insulating material disposed across the surface of the layer of semiconductor material; and an electrode overlying at least that portion of the layer of insulating material which overlies the intervening region of the substrate.
Claim 19
Dependent Claim 21 words
The structure of claim 15 characterized in that the first and the second regions each comprise an oxide of the substrate.
Claim 20
Dependent Claim 21 words
The structure of claim 15 or 16 characterized in that the layer of insulating material comprises an oxide of the substrate.
Claim 21
Dependent Claim 15 words
The structure of claim 15, 16 or 17 characterized in that the substrate comprises silicon.
Claim 22
Dependent Claim 18 words
The structure of any one of clams 15-18 characterized in that the electrode comprises electrically conductive polycrystalline silicon.
Claim 23
Dependent Claim 18 words
The structure of any one of clams 15-18 characterized in that the electrode comprises electrically conductive polycrystalline silicon.
Claim 24
Dependent Claim 35 words
The structure of any one of claims 15-19 characterized in that the layer of insulating material is thicker over the first and the second spaced apart regions than over the intervening region of the substrate.
Claim 25
Dependent Claim 17 words
The structure of claim 20 characterized in that the electrode comprises N conductivity type doped polycrystalline silicon.
Claim 26
Dependent Claim 30 words
The structure of any one of claims 15-21 characterized in that glass is formed over the first and the second spaced apart regions and beneath the layer of semiconductor material.
Claim 27
Dependent Claim 19 words
The structure of claim 22 or 23 characterized in that the layer of glass comprises a source of impurity.
Claim 28
Dependent Claim 18 words
The structure of claim 22 or 23 characterized in that the glass comprises P 2 O 5 .
Claim 29
Dependent Claim 44 words
The structure of any one of claims 15-25 characterized in that a layer of electrically conductive material is deposited between the first spaced apart region and the layer of semiconductor material, and between the second spaced apart region and the layer of semiconductor material.
Claim 30
Dependent Claim 22 words
The structure of claim 25 characterized in that a layer of polycrystalline silicon is disposed over the layer of electrically conductive material.
Claim 31
Dependent Claim 16 words
The structure of claim 25 or 26 characterized in that the electrically conductive material comprises tantalum.
Claim 32
Dependent Claim 30 words
The structure of any one of claims 23-27 characterized in that the layer of glass comprises a source of impurity for doping selected regions of the layer of semiconductor material.
Claim 33
Dependent Claim 36 words
The structure of claim 28 characterized in that the selected regions of the layer of semiconductor material do not include that portion of the layer of semiconductor material disposed across the intervening region of the substrate.
Claim 34
Dependent Claim 36 words
The structure of any one of claims 22-29 characterized in that said layer of semiconductor material comprises silicon which is monocrystalline where disposed on the substrate and polycrystalline where disposed on the at least one layer;

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