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EP0077147A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Monitor unit for data processor

Assignee: Bull HN Information Systems Inc
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Filing: 1982-09-29
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Granted: —
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Expires: 2002-09-29
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Abstract

Abstract A hardware monitoring interface unit (HMIU) 4 is coupled to a data processing unit 1 and receives all information transferred between subsystems (10, 12, 16-1 to 16-n) of the data processing unit over the system bus 2. Programmable hit matrices (PHM's) include input latches for receiving the information, memory circuits for storing binary ONE' S in locations addressed by predetermined portions of the information, and output latches for storing the binary ONE's or "hit" signals read from the memory circuits. The "hit" signals are plug-wired into logic circuits and counters in a monitor 6 to collect statistical data. The HMIU 4 includes a multiplexer for switching monitoring between the system bus 2 and a "private" cache memory bus 20 coupling the CPU 10 direct to a cache memory 8.

Inventors

  • 👤 Richard P. Wilder, Jr.

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 00:25
CPC Classifications
G; G06; G06F; G06F9/00; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G06F11/349

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 139 words
A data processing system (1) including a memory subsystem (12), a plurality of I/O controllers (16-1 to 16-n), and a central processor unit (10) all coupled to a system bus (2), a monitor interface unit (4), coupled to the system bus, which generates hit signals in response to predetermined combinations of system bus signals representative of information being transferred between the subsystem of the data processing system, and a monitor (6) coupled to the monitor interface unit and responsive to the hit signals to generate performance data, characterized in that the monitor interface unit (4) comprises a plurality of programmable his matrices (42, 45; PHMO-8), each responsive to a respective set of system bus signals to generate one of the his signals (PCMOHO, etc.) when that set is part of any of said predetermined combinations of system bus signals.
Claim 2
Dependent Claim 139 words
A data processing system (1) including a memory subsystem (12), a plurality of I/O controllers (16-1 to 16-n), and a central processor unit (10) all coupled to a system bus (2), a monitor interface unit (4), coupled to the system bus, which generates hit signals in response to predetermined combinations of system bus signals representative of information being transferred between the subsystem of the data processing system, and a monitor (6) coupled to the monitor interface unit and responsive to the hit signals to generate performance data, characterized in that the monitor interface unit (4) comprises a plurality of programmable his matrices (42, 45; PHMO-8), each responsive to a respective set of system bus signals to generate one of the his signals (PCMOHO, etc.) when that set is part of any of said predetermined combinations of system bus signals.
Claim 3
Dependent Claim 60 words
A data processing system according to Claim 1, characterized in that each programmable hit matrix comprises a random access memory having a plurality of rows addressed by the respective set of system bus signals and a plurality of columns each of which can have hit signals stored therein corresponding to different ones of the predetermined combinations of system bus signals.
Claim 4
Dependent Claim 60 words
A data processing system according to Claim 1, wherein the central processing unit (2) is coupled to a cache memory unit (8) by means of a cache bus (20), characterized in that the monitor interface unit is fed also with the cache bus signals, and includes multiplexing means for selecting either the system bus signals or the cache bus signals.

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