EP0075651A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Flat panel display devices
Assignee: International Business Machines Corp
•
Filing: 1982-06-02
•
Granted: —
•
Expires: 2002-06-02
Abstract
Abstract A flat panel display device comprises a matrix (10) of X and Y drive lines and a plurality of selecting field effect transistors (12). Each FET (12) is selectively operable by applying a potential across an individual pair of X and Y drive lines for controlling activation of a corresponding optical transducer (14). A high value resistor (15) is interposed in series between the gate electrode (G) of each selecting FET (12) and associated drive line to minimize the effect a short circuit caused by a defective gate electrode establishing an electrical connection between X and Y drive lines. The resistance is preferably provided by a segment of undoped polysilicon in a polysilicon circuit line connecting each gate electrode with the associated X drive line.
Inventors
- 👤 Steven Wade Depp
- 👤 Anthony Juliana, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 18:07
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/38; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; G09G3/36; G09G3/3611; G09G3/3648; G02F1/136213; G02F1/136259; G02F1/136268; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0842; G09G2330/00; G09G2330/08
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
171 words
1 A flat panel display device of the line-at-a-time addressed type comprising a set (X I -X n ) of X drive lines and a set (Y1 n) of Y drive lines arranged in overlying spaced relationship to form an X-Y matrix, and a plurality of field effect transistors (FETs), each FET (12;12') selectively operable by applying a potential across an individual pair of X and Y drive lines for controlling activation of a corresponding optical transducer (14;14'), each FET including a gate electrode (G) connected to a drive line of one of the sets of drive lines, and two other electrodes (S,D) operationally connected respectively to a drive line of the other set of drive lines and to an individual optical transducer (14), characterized by high value resistance means (15;15') interposed in series between each gate electrode (G) and the associated drive line of the one set to minimize the effect a short circuit caused by a defective gate electrode establishing an electrical connection between X and Y drive lines.
Claim 2
Dependent Claim
171 words
1 A flat panel display device of the line-at-a-time addressed type comprising a set (X I -X n ) of X drive lines and a set (Y1 n) of Y drive lines arranged in overlying spaced relationship to form an X-Y matrix, and a plurality of field effect transistors (FETs), each FET (12;12') selectively operable by applying a potential across an individual pair of X and Y drive lines for controlling activation of a corresponding optical transducer (14;14'), each FET including a gate electrode (G) connected to a drive line of one of the sets of drive lines, and two other electrodes (S,D) operationally connected respectively to a drive line of the other set of drive lines and to an individual optical transducer (14), characterized by high value resistance means (15;15') interposed in series between each gate electrode (G) and the associated drive line of the one set to minimize the effect a short circuit caused by a defective gate electrode establishing an electrical connection between X and Y drive lines.
Claim 3
Dependent Claim
38 words
2 A device according to claim 1, characterized in that the resistance means comprises a segment of undoped polysilicon in a polysilicon circuit line connecting each gate electrode with one of the drive lines of said one set.
Claim 4
Dependent Claim
25 words
3 A device according to claim 2, in which the segment of the polysilicon circuit line is covered by a mask (32) prior to doping.
Claim 5
Dependent Claim
30 words
4 A display device according to claim 2 or 3, in which the magnitude of the high value resistance provided by the segment is preselected by controlling the aspect ratio.
Claim 6
Dependent Claim
35 words
5 A device according to any preceding claim, in which the electrode of each FET that is connected to the optical transducer is also connected in parallel to ground via a capacitor (13;13 1 ).
Claim 7
Dependent Claim
114 words
6 A device according to claim 5, characterized in that each of the FETs is a selecting FET (121) having associated therewith a respective driving FET (20), the gate electrode (G) of each driving FET (20) being connected in parallel to one of the two other electrodes of a selecting FET (12') and to a ground via the capacitor (13'), and one of the other two electrodes of the driving FET being connected in parallel to ground and to one terminal of the optical transducer (14'), the other of the other driving FET electrodes being connected in parallel to the other terminal of the optical transducer and to a source (22) of alternating potential.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.