EP0074215A2
Expired / Lapsed
EP
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CMOS devices with self-aligned channel stops
Assignee: Raytheon Co
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Filing: 1982-08-25
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Granted: —
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Expires: 2002-08-25
Abstract
Abstract An improved process is provided for fabricating CMOS (Complementary Metal Oxide Semiconductor) devices formed on a semiconductor substrate having n-channel and p-channel regions of n- and p-type conductivity, respectively. Conventional source, drain and gate portions are formed in the regions and electrical contacts are made thereto. The improvement comprises providing self-aligned channel stops between regions of the same conductivity and between regions of the opposite conductivity. The channel stops between regions of the opposite conductivity are mutually self-aligned. The self-alignment is achieved by use of a single mask, called a "complementary" mask. The process of the invention permits fabrication of submicrometer devices.
Inventors
- 👤 John Y. Chen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:43
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/95
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
62 words
A process for fabricating CMOS devices formed on a semiconductor substrate provided with n-channel and p-channel regions of n- and p-type conductivity, respectively, which includes forming source, drain and gate portions in said regions and making electrical contacts to said portions, wherein the improvement comprises forming self-aligned channel stops between regions of the same conductivity and between regions of the opposite conductivity.
Claim 2
Dependent Claim
62 words
A process for fabricating CMOS devices formed on a semiconductor substrate provided with n-channel and p-channel regions of n- and p-type conductivity, respectively, which includes forming source, drain and gate portions in said regions and making electrical contacts to said portions, wherein the improvement comprises forming self-aligned channel stops between regions of the same conductivity and between regions of the opposite conductivity.
Claim 3
Dependent Claim
19 words
The process of Claim 1 in which the channel stops between regions of the opposite conductivity are mutually self-aligned.
Claim 4
Dependent Claim
105 words
The process of Claim 1 in whch the self-aligned channel stops are formed by a process which includes: a) opening windows for both n- and p-channel devices in an oxide layer formed on the semiconductor substrate; b) forming a complementary mask to cover p-channel devices by a composite resist mask and implanting ions to form n-channel devices; c) evaporating a metal layer on both the composite resist mask and the n-channel devices; d) lifting off those portions of the metal layer covering the composite resist mask; and e) implanting ions to form p-channel devices using the remaining portions of the metal layer as a mask.
Claim 5
Dependent Claim
16 words
The process of Claim 3 in which the complementary resist mask comprises at least two layers.
Claim 6
Dependent Claim
24 words
The process of Claim 4 in which the comple- m entary resist mask is at least about twice as thick as the metal layer.
Claim 7
Dependent Claim
42 words
The process of Claim 5 in which the complementary resist mask comprises a'thick layer of photoresist about 2 µm thick formed on the substrate and a thin layer of photoresist about 0.5 to 1 µm thick formed on the thick photoresist layer.
Claim 8
Dependent Claim
35 words
The process of Claim 5 in which the complementary resist mask comprises a thick layer of polysilicon about 1 µm thick and a thin layer of photoresist about 0.5 to 1 µm thick formed thereon.
Claim 9
Dependent Claim
54 words
The process of Claim 5 in which the complementary resist mask comprises a thick layer of photoresist about 2 µm thick formed on the substrate, a thin metal layer about 1,000 A thick formed on the thick photoresist layer and a thin phtotresist layer about 0.5 to 1 µm formed on the metal layer.
Claim 10
Dependent Claim
19 words
The process of Claim 3 in which the semiconductor substrate comprises silicon and the oxide layer comprises silicon dioxide.
Claim 11
Dependent Claim
34 words
The process of Claim 9 in which boron atoms are implanted in the substrate to form p-wells and p +- channel stops and phosphorus atoms are implanted in the p-wells to form n-channel devices.
Claim 12
Dependent Claim
34 words
The process of Claim 9 in which phosphorus atoms are implanted in the substrate to form n-wells and n +- channel stops and boron atoms are implanted in the n-wells to form p-channel devices.
Claim 13
Dependent Claim
29 words
The process of Claim 3 in which the ions are implanted under conditions such that the peak distribution of atoms lies in the substrate just beneath the oxide layer.
Claim 14
Dependent Claim
23 words
The process of Claim 3 in which the metal layer is formed to a thickness that is an inverse function of its density.
Claim 15
Dependent Claim
22 words
The process of Claim 13 in which the metal layer comprises about 5,000 A of aluminum or about 2,500 A of gold.
Claim 16
Dependent Claim
8 words
Product produced by the process of Claim 1.
References Cited (Backward Citations)
No citation records indexed.
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