EP0073726A2
Expired / Lapsed
EP
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Semi-conductor memory circuit
Assignee: Fujitsu Ltd
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Filing: 1982-08-31
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Granted: —
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Expires: 2002-08-31
Abstract
Abstract A semiconductor memory circuit including a pair of feedback means. The feedback means are connected between pairs of conventional bit lines and control gates of conventional load transistors. The feedback means control the on or off state of these load transistors in accordance with the logic states of the pair of bit lines.
Inventors
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 18:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
110 words
A semiconductor memory circuit comprising at least a pair of bit lines; a memory cell to be connected to the pair of bit lines; a pair of load transistors to be inserted between a power source and the corresponding bit lines; and a word line for accessing the memory cell, characterized in that a pair of feedback means is introduced into the semiconductor memory circuit, the feedback means are connected between the pair of bit lines and control gates of the pair of load transistors, and the feedback means control the on or off state of the load transistors in accordance with logic states of the pair of bit lines.
Claim 2
Dependent Claim
110 words
A semiconductor memory circuit comprising at least a pair of bit lines; a memory cell to be connected to the pair of bit lines; a pair of load transistors to be inserted between a power source and the corresponding bit lines; and a word line for accessing the memory cell, characterized in that a pair of feedback means is introduced into the semiconductor memory circuit, the feedback means are connected between the pair of bit lines and control gates of the pair of load transistors, and the feedback means control the on or off state of the load transistors in accordance with logic states of the pair of bit lines.
Claim 3
Dependent Claim
58 words
A semiconductor memory circuit as set forth in claim 1, wherein the pair of feedback means is comprised of a pair of level converters, each of the level converters converting the voltage of the corresponding bit line so as to apply the converted voltage to the control gate of the load transistor connected to the same bit line.
Claim 4
Dependent Claim
58 words
A semiconductor memory circuit as set forth in claim 1, wherein the pair of feedback means is comprised of a pair of level converters, each of the level converters inverting the voltage of the corresponding bit line so as to apply the inverted voltage to the control gate of the load transistor connected to the other bit line.
Claim 5
Dependent Claim
21 words
A semiconductor memory circuit as set forth in claim 2, level converters each being fabricated by two inverters connected in cascade.
Claim 6
Dependent Claim
20 words
A semiconductor memory circuit as set forth in claim 3, each of the level converters being fabricated by an inverter.
Claim 7
Dependent Claim
93 words
A semiconductor memory circuit as set forth in claim 1, wherein each transistor comprising the memory cell is either a p-channel or n-channel transistor and each corresponding load transistor is the other conductivity channel transistor and the pair of feedback means is comprised of two wirings, one wiring being connected between one bit line and the control gate of the load transistor connected to the other bit line and the other wiring being connected between the other bit line and the control gate of the load transistor connected to said one bit line.
Claim 8
Dependent Claim
64 words
A semiconductor memory circuit as set forth in claim 1, wherein a pair of gate means is further introduced in the semiconductor memory circuit, the pair of gate means being controlled by a gate pulse and operating to stop the supply of the power source to the bit lines, during a predetermined short interval, immediately after the operation for accessing the memory cell commences.
Claim 9
Dependent Claim
32 words
A semiconductor memory circuit as set forth in claim 7, wherein each of the pair of gate means is inserted between the power source and each of the pair of load transistors.
Claim 10
Dependent Claim
58 words
A semiconductor memory circuit as set forth in claim 7, wherein each of the gate means is combined with the corresponding feedback means so as to create a logic gate having an output to be connected the control gate of the corresponding one load transistor, whereby the pair of feedback means are made active by the gate pulse.
Claim 11
Dependent Claim
105 words
A semiconductor memory circuit as set forth in claim 7 or 8, wherein another pair of gate means is introduced in the semiconductor memory circuit, acting as second gate means commonly controlled by a second gate pulse, in addition to said pair of gate means, acting as first gate means commonly controlled by the first said gate pulse, the second gate means being connected between the power source and corresponding bit line and being turned on by the second gate pulse generated at almost the same time as the first gate pulse but with a pulse width smaller than that of the first gate pulse.
Claim 12
Dependent Claim
44 words
A semiconductor memory circuit as set forth in claim 9, wherein a third gate means is further introduced in the semiconductor memory circuit, the third gate means being connected between the pair of bit lines and being turned on by the second gate pulse.
References Cited (Backward Citations)
No citation records indexed.
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