EP0073424A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Central processing unit for executing instructions of variable length
Assignee: Hitachi Ltd
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Filing: 1982-08-19
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Granted: —
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Expires: 2002-08-19
Abstract
Abstract A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
Inventors
- 👤 Yasushi Fukunaga
- 👤 Tadaaki Bandoh
- 👤 Kotaro Hirasawa
- 👤 Hidekazu Matsumoto
- 👤 Jushi Ide
- 👤 Takeshi Katoh
- 👤 Hiroaki Nakanishi
- 👤 Tetsuya Kawakami
- 👤 Ryosei Hiraoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 23:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30149; G06F9/30152
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
255 words
A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands, comprising: (A) instruction fetch means (25) for fetching an instruction from memory means storing instructions and operands, (B) decoding means (27) connected to said instruction fetch means (25) and for decoding an operation code and an operand specifier, (C) address calculating means (28) connected to said decoding means (25) and for calculating an address of an operand on the basis of the decoded result of the operand specifier from said decoding means, (D) operand fetch means (29) connected to said address calculating means (28) and for fetching the operand from said memory means on the basis of the calculated address, and (E) executing means (30) connected to said operand fetch means (29) as well as said decoding means (27) and for executing the instruction successively by the use of the operands from said operand fetch means (29) and in accordance with the decoded results of the operation codes from said decoding means (27), said decoding means (27) including: (i) operation code decoding means (63, 65) for decoding the operation codes of the instruction and delivering information on the operands in operand unit, and (ii) operand specifier decoding means (66) for decoding information added to specific fields of the respective operand specifiers, on whether or not the particular operand specifier is the last operand specifier.
Claim 2
Dependent Claim
255 words
A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands, comprising: (A) instruction fetch means (25) for fetching an instruction from memory means storing instructions and operands, (B) decoding means (27) connected to said instruction fetch means (25) and for decoding an operation code and an operand specifier, (C) address calculating means (28) connected to said decoding means (25) and for calculating an address of an operand on the basis of the decoded result of the operand specifier from said decoding means, (D) operand fetch means (29) connected to said address calculating means (28) and for fetching the operand from said memory means on the basis of the calculated address, and (E) executing means (30) connected to said operand fetch means (29) as well as said decoding means (27) and for executing the instruction successively by the use of the operands from said operand fetch means (29) and in accordance with the decoded results of the operation codes from said decoding means (27), said decoding means (27) including: (i) operation code decoding means (63, 65) for decoding the operation codes of the instruction and delivering information on the operands in operand unit, and (ii) operand specifier decoding means (66) for decoding information added to specific fields of the respective operand specifiers, on whether or not the particular operand specifier is the last operand specifier.
Claim 3
Dependent Claim
56 words
A central processing unit according to claim 1, wherein said decoding means (27) includes means (65) for deciding that the decoding of one instruction has ended, upon receiving the information indicative of the last operand from said operation code decoding means and the information indicative of the last operand specifier from said operand specifier decoding means.
Claim 4
Dependent Claim
62 words
A central processing unit according to claim 1, wherein said decoding means includes means (65) for causing the operand specifier to be used again, in a case where when the information indicative of the last operand specifier has been received from said operand specifier decoding means, the information indicative of the last operand is not received from said operation code decoding means.
Claim 5
Dependent Claim
63 words
A central processing unit according to claim 1, wherein said decoding means (27) includes error detection means for detecting the instruction as an error, in a case where when the information indicative of the last operand has been received from said operation code decoding means (66), said operand specifier decoding means (66) does not receive the information indicative of the last operand specifier.
Claim 6
Dependent Claim
43 words
A central processing unit according to claim 1, wherein said decoding means (27) includes means (83) for supplying said instruction fetch means with a signal for obtaining the operand specifier to be decoded next, each time the decoding of one operand specifier ends.
Claim 7
Dependent Claim
67 words
A central processing unit according to claim 1, wherein the instruction is formed of the operation code of one to plural bytes and the operand specifier of one to plural bytes, and said operand specifier decoding means (66) includes means for decoding the first byte of said each operand specifier and delivering the information on whether or not the particular operand specifier is the last operand specifier.
References Cited (Backward Citations)
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