Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits

Claim 2

Integrated circuit structure comprising: a monocrystalline silicon body (2); a pattern of dielectric isolation surrounding regions of said monocrystalline silicon in body (2); said pattern including a recessed dielectric portion (_22, 24) at the surface of the integrated circuit and a deep portion (20) which extends from the side of said recessed portion opposite to that portion at the surface of said body into the monocrystalline silicon body; and the deep portion (20) being substantially composed of polycrystalline silicon.

Claim 3

Integrated circuit structure of claim 1, characterized in that certain of the deep portions (20) of said pattern of dielectric isolation reaches the surface of silicon body (2) whereon the interconnecting metallurgy of said structure is located, that the polycrystalline silicon is highly doped and electrical contact is made to certain of the deep portions (20) at said surface so as to form a substrate contact to silicon body (20) throughout the pattern of said deep portions (20).

Claim 4

Integrated circuit structure of claim 1, characterized in that silicon body (2) includes a silicon substrate (2), an epitaxial layer (4) and a subcollector region (6) which overlaps substrate (2) and layer (4).

Claim 5

Integrated circuit structure of claim 1, characterized in that a bipolar transistor or a field effect transistor is located in at least some of said regions of monocrystalline silicon.

Claim 6

Integrated circuit structure of claim 1, characterized in that recessed dielectric portion (22, 24) is greater than 1 µm in width and less than 1.5 pm in depth, and composed of thermally grown silicon dioxide.

Claim 7

Integrated circuit structure of claim 1, characterized in that the deep portion (20) is less than 5 µm in width and 6 pm in depth, and has substantially vertical sidewalls composed of silicon dioxide with polycrystalline silicon contained within the sidewalls of said deep portion (20).

Claim 8

Integrated circuit structure of claim 4, characterized in that the bipolar transistor is an NPN, the polycrystalline silicon is P+ and the silicon substrate is P.

Claim 9

Method for forming a recessed isolation structure for an integrated circuit structure having substrate contacts comprising: forming a pattern of trenches by reactive ion etching having substantially vertical sidewalls in a monocrystalline silicon substrate (24) in all areas where said isolation structure and said substrate contacts are desired by an etching procedure through an appropriate mask; forming an insulating layer (18) upon the surfaces of said trenches; removing insulating layer (18) from the bottom surfaces of said trenches by reactive ion etching; depositing a layer (20) of doped polycrystalline silicon over said substrate to fill said trenches; planarizing the substrate by a reactive ion etching process which substantially removes said layer of polycrystalline silicon except from said trenches; forming a masking layer over the substrate surface having said pattern of trenches filled with polycrystalline silicon; opening a pattern in said masking layer to the silicon substrate (4) wherein said isolation structure (22, 241 is desired and which is in at least part over said pattern of trenches filled with polycrystalline silicon (20); said pattern in said masking layer is open to the pattern of trenches except for the portion of the pattern of trenches designated to act as the substrate contacts of said integrated circuit structure; oxidizing the exposed monocrystalline substrate having said pattern of trenches filled with polycrystalline silicon to produce said recessed isolation structure (22, 24); removing said masking layer; forming the desired active and passive devices (34, 36, 38) in said monocrystalline silicon substrate (4) between said recessed isolation structure (22, 24);and making appropriate electrical contact to said active and passive devices, and said substrate contacts.

Claim 10

Method for forming a recessed isolation structure for an integrated circuit structure having substrate contacts comprising: forming a pattern of trenches by reactive ion etching having substantially vertical sidewalls in a monocrystalline silicon substrate (24) in all areas where said isolation structure and said substrate contacts are desired by an etching procedure through an appropriate mask; forming an insulating layer (18) upon the surfaces of said trenches; removing insulating layer (18) from the bottom surfaces of said trenches by reactive ion etching; depositing a layer (20) of doped polycrystalline silicon over said substrate to fill said trenches; planarizing the substrate by a reactive ion etching process which substantially removes said layer of polycrystalline silicon except from said trenches; forming a masking layer over the substrate surface having said pattern of trenches filled with polycrystalline silicon; opening a pattern in said masking layer to the silicon substrate (4) wherein said isolation structure (22, 241 is desired and which is in at least part over said pattern of trenches filled with polycrystalline silicon (20); said pattern in said masking layer is open to the pattern of trenches except for the portion of the pattern of trenches designated to act as the substrate contacts of said integrated circuit structure; oxidizing the exposed monocrystalline substrate having said pattern of trenches filled with polycrystalline silicon to produce said recessed isolation structure (22, 24); removing said masking layer; forming the desired active and passive devices (34, 36, 38) in said monocrystalline silicon substrate (4) between said recessed isolation structure (22, 24);and making appropriate electrical contact to said active and passive devices, and said substrate contacts.

Claim 11

Method of claim 8, characterized in that said monocrystalline silicon substrate includes a base silicon body (.2) and an epitaxial layer (4) thereover.

Claim 12

Method of claim 8, characterized in that said devices are a bipolar integrated circuit structure, which is formed in the substrate by providing a subcollector (61 overlaping said base silicon body (2) and said epitaxial layer (4) and by forming a bipolar transistor within said monocrystalline substrate between said recessed isolation structure.

Claim 13

Method of claim 8, characterized in that the insulating layer (18) on the surfaces of the trenches is of silicon dioxide which is formed by thermal oxidation.

Claim 14

Method of claim 8, characterized in that prior to the oxidizing step the exposed monocrystalline substrate is etched so that when the oxidizing is completed the top surfaces of the formed silicon dioxide (22, 24) will be substantially planar with the surface of said monocrystalline substrate (4).