§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0073149A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor chip mounting module

Assignee: Unisys Corp
•
Filing: 1982-08-20
•
Granted: —
•
Expires: 2002-08-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A packaging and interconnection module for semiconductor chips comprises a ceramic base substrate (12, 13) for the chips (11, 11') the substrate being provided with lead-out pins (15). Within the ceramic base substrate is a processing substrate (19) bearing insulating film layers carrying patterns of interconnection conductors with vias corresponding in position to the pins (15). One layer of the processing substrate constitutes a ground plane. The terminals of the chips (11, 11') are connected to pads formed on the conductors of the upper layer of the processing substrate. Connections to the vias in the processing substrate may be made by solder bumps. Generally two layers of interconnection conductors extending generally perpendicular to each other will be sufficient for interconnecting the chips. This method allows thin film technology to be used for manufacturing the processing substrate. It permits close spacing of the chips with short conductive paths in a material of low dielectric constant.

Inventors

  • 👤 Thomas Peter Currie
  • 👤 Norman Dr. Goldberg

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 01:00
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/153; H10W72/00; H10W72/071; H10W72/075; H10W72/20; H10W72/29; H10W72/50; H10W72/531; H10W72/5363; H10W72/90; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 99 words
A packaging and interconnection module for semiconductor chips comprising a ceramic base substrate carrying the chips, provided with lead-out pins and sealed by a lid, characterised in that the ceramic base substrate (12) also carries a processing substrate (19) with insulating film layers bearing a pattern of interconnection conductors (33, 37) with vias (18) corresponding in position to the pins (15) in the ceramic base substrate (12) and with one layer (28) bearing a ground plane (26) insulated from the vias (18), and the terminals of the chips are connected to pads (38) formed on the conductors (33, 37).
Claim 2
Dependent Claim 99 words
A packaging and interconnection module for semiconductor chips comprising a ceramic base substrate carrying the chips, provided with lead-out pins and sealed by a lid, characterised in that the ceramic base substrate (12) also carries a processing substrate (19) with insulating film layers bearing a pattern of interconnection conductors (33, 37) with vias (18) corresponding in position to the pins (15) in the ceramic base substrate (12) and with one layer (28) bearing a ground plane (26) insulated from the vias (18), and the terminals of the chips are connected to pads (38) formed on the conductors (33, 37).
Claim 3
Dependent Claim 58 words
A packaging and interconnection module for semiconductor chips according to claim 1, in which there are two layers bearing interconnection conductors (33, 37), the first layer being of closely-spaced conductive lines extending generally in a first direction and the second layer being of closely-spaced conductive lines extending in a direction generally orthogonal to those of the first layer.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag