A MIS device and a method of manufacturing it

Claim 3

A method according to claim 1, wherein the protection element forming region (13) is provided during the step of forming an MIS transistor.

Claim 4

A method according to claim 1 or claim 2, comprising the steps of forming a field insulation film (15,15 ! ) having windows for exposing a transistor-forming region (12) and a protection element forming region (13) on the semiconductor substrate (11); forming the gate electrode (16) on the transistor-forming region (12) and selectively introducing an impurity into the surface of the substrate (11) at the protection element forming region (13) and the transistor-forming region (12) using the gate electrode (16) as a mask so as to form a source region (17a), a drain region (17b) and a protection element region (17c); forming a lower insulation film (18) on the field insulation film (15,15') and forming contact windows (19a,19b,19c) at portions on the source region (17a), the drain region (17b),the gate electrode (16), and the protection element region (17o); forming, on the lower insulation film, a lower layer wiring pattern including a lower source wiring (20a),a lower drain wiring (20b), and the lower gate wiring (20c) which are connected via respective contact windows (19a, 19b, 19d, 19c) to the source region (17a), the drain region (17b), and between the gate electrode (16) and the protection element region (17c) respectively; forming, on the lower layer wiring pattern , a second insulation film (21); forming on the second insulation film (21), a wiring connection window (22) so as to expose a part of the lower gate wiring (20c); and connecting the upper layer wiring pattern (23) to the lower gate wiring (20c) via the wiring connection window (22).

Claim 5

A method according to claim 1 or claim 2, comprising the steps of forming a field insulation film (15,15 ! ) having windows for exposing a transistor-forming region (12) and a protection element-forming region (13) on the semiconductor substrate; forming the gate electrode (16) on the transistor-forming region (12) and forming a masking film (32) on the protection element forming region (13); selectively injecting impurity ions into the transistor forming region (12) using the gate electrode (16) as a mask, so as to form a source region and a drain region; forming a lower insulation film (18) on the substrate (11) and forming contact windows (19a, 19b,19d, 19c) at portions on the source region (17a), the drain region (17b), the gate electrode (16), and the protection element-forming region (17c) respectively; forming, on the lower insulation film, a lower layer wiring pattern including a lower source wiring (20a), a lower drain wiring (20b) and the lower gate wiring (20c) which are connected via respective contact windows to the source region (17a),the drain region (17b), and between the gate electrode (16) and the protection element-forming region (13) respectively; forming, on the lower layer wiring pattern,a second insulation film (21); forming in the second insulation film (21), a wiring connection window (22) so as to expose a part of the lower gate wiring (20c); and connecting the upper layer wire pattern (23) to the lower gate wiring (20c) via the wiring connection window (22).

Claim 7

A method according to claim 5, wherein the protection element is disconnected during connection of the upper layer wiring pattern (23) to another functional element.

Claim 8

A method according to claim 5 or claim 6, when dependant on claim 3 or claim 4, wherein the wiring connection window (22) is formed in the second insulation film (21) at a position such that the upper layer wiring pattern (23) is connected to the lower gate wiring (20c) between the gate electrode (16) and the protection element, the method further comprising forming an etching window (45) in the second insulating film (21); and etching selectively via the etching window (45) a portion of the lower gate between the upper/lower wiring pattern connection and the protection element region (13) to disconnect the gate electrode (16) from the protection element.

Claim 9

An MIS device having a multilayer wiring structure, the device comprising a semiconductor substrate (11); an MIS transistor having a gate insulation film (15) formed on the substrate (11) and a gate electrode (16) formed on the gate insulation film (15); a lower layer wiring pattern (20c) connected to the gate electrode (16) of the MIS transistor; a protection element (17c) connected between the lower layer wiring pattern (20c) and the semiconductor substrate (11), at least during manufacture of the device,the protection element (17c) having a conduction voltage smaller than the dielectric strength of the gate insulation film (15) of the MIS transistor; and an upper layer wiring pattern (23) connected to the lower layer wiring pattern (20c), whereby the lower layer wiring pattern (20c) is connected only to the gate electrode (16) and the upper layer wiring pattern (23), and the protection element .(17c) at least during formation of the device.

Claim 10

An MIS device having a multilayer wiring structure, the device comprising a semiconductor substrate (11); an MIS transistor having a gate insulation film (15) formed on the substrate (11) and a gate electrode (16) formed on the gate insulation film (15); a lower layer wiring pattern (20c) connected to the gate electrode (16) of the MIS transistor; a protection element (17c) connected between the lower layer wiring pattern (20c) and the semiconductor substrate (11), at least during manufacture of the device,the protection element (17c) having a conduction voltage smaller than the dielectric strength of the gate insulation film (15) of the MIS transistor; and an upper layer wiring pattern (23) connected to the lower layer wiring pattern (20c), whereby the lower layer wiring pattern (20c) is connected only to the gate electrode (16) and the upper layer wiring pattern (23), and the protection element .(17c) at least during formation of the device.

Claim 11

An MIS device according to claim 8, wherein the protection element (17c) comprises a reverse junction formed between the lower layer wiring pattern (20c) and the semiconductor substrate (11) of the MIS device.

Claim 12

An MIS device according to claim 8, wherein the protection element comprises a Schottky barrier formed between the lower layer wiring pattern (20c) and the semiconductor substrate (11) of the MIS device.