EP0071743A2
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EP
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Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
Assignee: International Business Machines Corp
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Filing: 1982-06-29
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Granted: —
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Expires: 2002-06-29
Abstract
Abstract In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.
Inventors
- 👤 James Arthur Brewer
- 👤 Lewis Clark Eggebrecht
- 👤 David Allen Kummer
- 👤 Patricia Price Mchugh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 14:00
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
158 words
Data processing system having a system bus for transferring address, data and control information among a central processing unit which produces a system clock signal, a programmable direct memory access controller which has a plurality of prioritized channels each of which contains the functions of a memory address register and counter, a central processing unit/direct memory access cycle arbitration circuit, and a central processing unit/direct memory access address bus multiplexer; a plurality of input/output devices having access to the bus via the direct access memory controller; and a dynamic memory which requires periodic refreshing within predetermined minimum time intervals; characterized in that it comprises : memory refresh request signal generating means, coupled between the central processing unit and the highest priority channel of the direct memory access controller, and responsive to the system clock signal for periodically applying memory refresh request signals to said highest priority channel to initiate memory refresh cycles within said predetermined minimum time intervals.
Claim 2
Dependent Claim
158 words
Data processing system having a system bus for transferring address, data and control information among a central processing unit which produces a system clock signal, a programmable direct memory access controller which has a plurality of prioritized channels each of which contains the functions of a memory address register and counter, a central processing unit/direct memory access cycle arbitration circuit, and a central processing unit/direct memory access address bus multiplexer; a plurality of input/output devices having access to the bus via the direct access memory controller; and a dynamic memory which requires periodic refreshing within predetermined minimum time intervals; characterized in that it comprises : memory refresh request signal generating means, coupled between the central processing unit and the highest priority channel of the direct memory access controller, and responsive to the system clock signal for periodically applying memory refresh request signals to said highest priority channel to initiate memory refresh cycles within said predetermined minimum time intervals.
Claim 3
Dependent Claim
107 words
Data processing system according to claim 1 characterized in that said refresh request signal generating means comprises : divider counter means, coupled to the central processing unit, and responsive to said system clock signal for generating a refresh clock signal having said predetermined time intervals; and latch means, coupled between said divider counter means and said highest priority channel, and responsive to the refresh clock signal for applying the refresh request signals to said highest priority channel; said latch means being periodically set by the refresh clock signal, and reset by an acknowledge signal from the direct memory access controller at the completion of each refresh cycle.
Claim 4
Dependent Claim
208 words
Data processing system according to claim 1 or 2 characterized in that the address bus and the data bus are connected to said dynamic random access memory to use in the performance of a memory operation at a selected location of said memory, each location being defined by an address code manifested by the signals on said address bus, each address code defining each location as the intersection of a row of locations and a column of locations in said memory, all memory locations in a row being refreshed by performing a memory operation upon any location in that row, and the highest priority channel of the direct memory access controller upon application thereto of a memory refresh request signal, acquires control of the address and data buses and causes a memory operation to be performed on a location in one row of memory locations, said divider counter means being incremented each time a refresh request signal is applied and storing a count which determines which row is to have said memory operation performed thereon, and the latch means provides memory refresh request signals at such a rate that all rows of locations have a memory refresh operation performed on a location therein within said certain time period.
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